Cypress CY7C1310BV18, CY7C1314BV18 Sales, Solutions, and Legal Information, Vkn/Pyrs, Usb

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Document History Page

Document Title: CY7C1310BV18/CY7C1910BV18/CY7C1312BV18/CY7C1314BV18, 18-Mbit QDR™-II SRAM 2-Word Burst

Architecture

Document Number: 38-05619

*E

1274723

See ECN

VKN

Corrected typo in the JTAG ID code for CY7C1910BV18

*F

2511674

06/03/08

VKN/PYRS

Updated Logic Block diagrams

 

 

 

 

Updated IDD/ISB specs

 

 

 

 

Added footnote# 19 related to IDD

 

 

 

 

Updated power up sequence waveform and its description

 

 

 

 

Changed DLL minimum operating frequency from 80 MHz to 120 MHz

 

 

 

 

Changed ΘJA spec from 28.51 to 18.7

 

 

 

 

Changed ΘJC spec from 5.91 to 4.5

 

 

 

 

Changed tCYC maximum spec to 8.4 ns for all speed bins

 

 

 

 

Modified footnotes 21 and 28

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products

 

PSoC Solutions

 

PSoC

psoc.cypress.com

General

psoc.cypress.com/solutions

Clocks & Buffers

clocks.cypress.com

Low Power/Low Voltage

psoc.cypress.com/low-power

Wireless

wireless.cypress.com

Precision Analog

psoc.cypress.com/precision-analog

Memories

memory.cypress.com

LCD Drive

psoc.cypress.com/lcd-drive

Image Sensors

image.cypress.com

CAN 2.0b

psoc.cypress.com/can

 

 

USB

psoc.cypress.com/usb

© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document #: 38-05619 Rev. *F

Revised June 2, 2008

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QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1310BV18Logic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1310BV18 2M x CY7C1910BV18 2M xWPS BWS CY7C1312BV18 1M xCY7C1314BV18 512K x NC/72M NC/36MPin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1Write Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1314BV18 follows Write cycle description table for CY7C1910BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05619 Rev. *F AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 26, 27 Switching WaveformsOrdering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN VKN/PYRS