Cypress CY7C1310BV18, CY7C1314BV18, CY7C1312BV18, CY7C1910BV18 manual Ordering Information

Page 25

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Ordering Information

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
250	CY7C1310BV18-250BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1910BV18-250BZC

	CY7C1312BV18-250BZC

	CY7C1314BV18-250BZC

	CY7C1310BV18-250BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-250BZXC

	CY7C1312BV18-250BZXC

	CY7C1314BV18-250BZXC

	CY7C1310BV18-250BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1910BV18-250BZI

	CY7C1312BV18-250BZI

	CY7C1314BV18-250BZI

	CY7C1310BV18-250BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-250BZXI

	CY7C1312BV18-250BZXI

	CY7C1314BV18-250BZXI

200	CY7C1310BV18-200BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1910BV18-200BZC

	CY7C1312BV18-200BZC

	CY7C1314BV18-200BZC

	CY7C1310BV18-200BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-200BZXC

	CY7C1312BV18-200BZXC

	CY7C1314BV18-200BZXC

	CY7C1310BV18-200BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1910BV18-200BZI

	CY7C1312BV18-200BZI

	CY7C1314BV18-200BZI

	CY7C1310BV18-200BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-200BZXI

	CY7C1312BV18-200BZXI

	CY7C1314BV18-200BZXI

Document #: 38-05619 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1310BV18Doff Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1310BV18 2M x CY7C1910BV18 2M xWPS BWS CY7C1312BV18 1M xCY7C1314BV18 512K x NC/72M NC/36MPin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1Write Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1314BV18 follows Write cycle description table for CY7C1910BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document # 38-05619 Rev. *F Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 26, 27 Switching WaveformsOrdering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramSYT Document HistoryNXR Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN VKN/PYRS