Cypress CY7C1310BV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1310BV18	CY7C1910BV18	CY7C1312BV18	CY7C1314BV18	Description
		CY7C1310BV18	CY7C1910BV18	CY7C1312BV18	CY7C1314BV18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010011010000101	11010011010001101	11010011010010101	11010011010100101	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	107

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do not use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do not use: This instruction is reserved for future use.

RESERVED	110	Do not use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document #: 38-05619 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1310BV18Logic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1310BV18 2M x CY7C1910BV18 2M xWPS BWS CY7C1312BV18 1M xCY7C1314BV18 512K x NC/72M NC/36MPin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1Write Cycle Descriptions Truth TableOperation CommentsWrite cycle description table for CY7C1314BV18 follows Write cycle description table for CY7C1910BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05619 Rev. *F AC Electrical CharacteristicsInput High Voltage Vref + Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 26, 27 Switching WaveformsOrdering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN VKN/PYRS