Cypress CY7C1312BV18, CY7C1314BV18, CY7C1310BV18, CY7C1910BV18 Boundary Scan Order, Bit # Bump ID

Page 18

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Boundary Scan Order

Bit #	Bump ID	Bit #	Bump ID	Bit #	Bump ID	Bit #	Bump ID
0	6R	27	11H	54	7B	81	3G

1	6P	28	10G	55	6B	82	2G

2	6N	29	9G	56	6A	83	1J

3	7P	30	11F	57	5B	84	2J

4	7N	31	11G	58	5A	85	3K

5	7R	32	9F	59	4A	86	3J

6	8R	33	10F	60	5C	87	2K

7	8P	34	11E	61	4B	88	1K

8	9R	35	10E	62	3A	89	2L

9	11P	36	10D	63	1H	90	3L

10	10P	37	9E	64	1A	91	1M

11	10N	38	10C	65	2B	92	1L

12	9P	39	11D	66	3B	93	3N

13	10M	40	9C	67	1C	94	3M

14	11N	41	9D	68	1B	95	1N

15	9M	42	11B	69	3D	96	2M

16	9N	43	11C	70	3C	97	3P

17	11L	44	9B	71	1D	98	2N

18	11M	45	10B	72	2C	99	2P

19	9L	46	11A	73	3E	100	1P

20	10L	47	Internal	74	2D	101	3R

21	11K	48	9A	75	2E	102	4R

22	10K	49	8B	76	1E	103	4P

23	9J	50	7C	77	2F	104	5P

24	9K	51	6C	78	3F	105	5N

25	10J	52	8A	79	1G	106	5R

26	11J	53	7A	80	1F

Document #: 38-05619 Rev. *F

Page 18 of 29

[+] Feedback

Image 18

Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1310BV18 Logic Block Diagram CY7C1910BV18Doff Logic Block Diagram CY7C1312BV18 Logic Block Diagram CY7C1314BV18CY7C1310BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1910BV18 2M xCY7C1314BV18 512K x CY7C1312BV18 1M xWPS BWS NC/72M NC/36MPin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance Sram #1Operation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1910BV18 followsWrite cycle description table for CY7C1314BV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05619 Rev. *F Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 26, 27Ordering Information 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History SYTNXR VKN Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS