Cypress CY7C1910BV18 manual Logic Block Diagram CY7C1312BV18, Logic Block Diagram CY7C1314BV18

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Logic Block Diagram (CY7C1312BV18)

18

D[17:0]

19Address

A(18:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[1:0]

Write Add. Decode

Write		Write
Reg		Reg
512K x		512K x	Decode
18 Array		18 Array	Read Add.
Read Data Reg.
	36	18
				Reg.
		18
				Reg.

Address Register

Control

Logic

Reg.

19 A(18:0)

RPS

C

C

CQ

18 CQ

18 18 Q[17:0]

Logic Block Diagram (CY7C1314BV18)

36

D[35:0]

18Address

A(17:0) Register

K

K CLK

Gen.

DOFF

VREF		Control
WPS
		Logic
BWS
	[3:0]

Write Add. Decode

Write		Write
Reg		Reg
256K x		256K x	Decode
36 Array		36 Array	Read Add.
Read Data Reg.
	72	36
				Reg.
		36
				Reg.

Address Register

Control

Logic

Reg.

18 A(17:0)

RPS

C

C

CQ

36 CQ

36 36 Q[35:0]

Document #: 38-05619 Rev. *F Page 3 of 29

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