Cypress CY7C1312BV18, CY7C1314BV18, CY7C1310BV18, CY7C1910BV18 manual 167

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1310BV18-167BZC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Commercial

	CY7C1910BV18-167BZC

	CY7C1312BV18-167BZC

	CY7C1314BV18-167BZC

	CY7C1310BV18-167BZXC	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-167BZXC

	CY7C1312BV18-167BZXC

	CY7C1314BV18-167BZXC

	CY7C1310BV18-167BZI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm)	Industrial

	CY7C1910BV18-167BZI

	CY7C1312BV18-167BZI

	CY7C1314BV18-167BZI

	CY7C1310BV18-167BZXI	51-85180	165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

	CY7C1910BV18-167BZXI

	CY7C1312BV18-167BZXI

	CY7C1314BV18-167BZXI

Document #: 38-05619 Rev. *F

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1310BV18Logic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1312BV18 Logic Block Diagram CY7C1314BV18CY7C1310BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1910BV18 2M xCY7C1314BV18 512K x CY7C1312BV18 1M xWPS BWS NC/72M NC/36MPin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance Sram #1Operation Truth TableWrite Cycle Descriptions CommentsDevice Write cycle description table for CY7C1910BV18 followsWrite cycle description table for CY7C1314BV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05619 Rev. *F AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 26, 27Ordering Information 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmNXR Document HistorySYT VKN Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS