Cypress CY7C1314BV18, CY7C1310BV18 manual Switching Waveforms, Read/Write/Deselect Sequence 26, 27

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CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [26, 27, 28]

READ	WRITE	READ	WRITE	READ	WRITE	NOP
1	2	3	4	5	6	7

WRITE NOP

tKH

RPS

WPS

AA0 tSA

tKL

tCYC

tKHKH

tSC	tHC
A2	A3
tSA tHA

D D10	D11		D30
			tSD
Q
			tCLZ
	tKHCH	tKL	tCO

D50

Q00

D51

tSD tHD

Q01 Q20

tDOH tCQDOH

D61

Q21 Q40

tCQD

Q41

tCHZ

CtKH

tKHCH	tKHKH	tCYC
tKHCH

tCCQO

tCQOH

tCCQO

tCQOH

CARE

UNDEFINED

Notes

26.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

27.Outputs are disabled (High-Z) one clock cycle after a NOP.

28.In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document #: 38-05619 Rev. *F

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1310BV18 Logic Block Diagram CY7C1910BV18Doff Logic Block Diagram CY7C1312BV18 Logic Block Diagram CY7C1314BV18Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1310BV18 2M x CY7C1910BV18 2M xCY7C1312BV18 1M x WPS BWSCY7C1314BV18 512K x NC/72M NC/36MPin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks Sram #1Truth Table Write Cycle DescriptionsOperation CommentsWrite cycle description table for CY7C1910BV18 follows Write cycle description table for CY7C1314BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document # 38-05619 Rev. *F Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Cypress Consortium Description 250 MHz 200 MHz 167 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 26, 27Ordering Information 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmDocument History SYTNXR Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsVKN VKN/PYRS