Cypress CY7C1910BV18, CY7C1314BV18 manual Switching Characteristics, Parameter Min Max, DLL Timing

Page 23

CY7C1310BV18, CY7C1910BV18

CY7C1312BV18, CY7C1314BV18

Switching Characteristics

Over the Operating Range [20, 21]

 

Cypress

Consortium

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

t

POWER

 

V (Typical) to the First Access [22]

1

 

1

 

1

 

ms

 

 

DD

 

 

 

 

 

 

 

tCYC

tKHKH

K Clock and C Clock Cycle Time

4.0

8.4

5.0

8.4

6.0

8.4

ns

tKH

tKHKL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) HIGH

1.6

2.0

2.4

ns

tKL

tKLKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input Clock (K/K

and C/C) LOW

1.6

2.0

2.4

ns

tKHKH

tKHKH

K Clock Rise to

 

 

Clock Rise and C to

 

Rise

1.8

2.2

2.7

ns

K

C

 

 

 

(rising edge to rising edge)

 

 

 

 

 

 

 

tKHCH

tKHCH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K/K

Clock Rise to C/C Clock Rise (rising edge to rising edge)

0

1.8

0

2.2

0

2.7

ns

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tAVKH

Address Setup to K Clock Rise

0.35

0.4

0.5

ns

tSC

tIVKH

Control Setup to K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0.35

0.4

0.5

ns

(RPS,

WPS)

tSCDDR

tIVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DDR Control Setup to Clock (K/K)

 

 

Rise

0.35

0.4

0.5

ns

 

 

 

(BWS0, BWS1, BWS3, BWS4)

 

 

 

 

 

 

 

tSD [23]

tDVKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.35

0.4

0.5

ns

D[X:0] Setup to Clock (K/K)

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

tKHAX

Address Hold after K Clock Rise

0.35

0.4

0.5

ns

tHC

tKHIX

Control Hold after K Clock Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

0.35

0.4

0.5

ns

(RPS,

WPS)

tHCDDR

tKHIX

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

 

Rise

0.35

0.4

0.5

ns

DDR Control Hold after

(K/K)

 

 

 

(BWS0, BWS1, BWS3, BWS4)

 

 

 

 

 

 

 

tHD

tKHDX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Rise

0.35

0.4

0.5

ns

D[X:0] Hold after Clock (K/K)

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

tCHQV

C/C

Clock Rise (or K/K

in Single Clock Mode) to Data Valid

0.45

0.45

0.50

ns

tDOH

tCHQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Rise

–0.45

–0.45

–0.50

ns

Data Output Hold after Output C/C

 

 

 

(Active to Active)

 

 

 

 

 

 

 

tCCQO

tCHCQV

 

 

 

Clock Rise to Echo Clock Valid

0.45

0.45

0.50

ns

C/C

tCQOH

tCHCQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Rise

–0.45

–0.45

–0.50

ns

Echo Clock Hold after C/C

tCQD

tCQHQV

Echo Clock High to Data Valid

0.30

0.35

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.30

–0.35

–0.40

ns

tCHZ

tCHQZ

 

 

 

 

 

Rise to High-Z (Active to High-Z) [24, 25]

 

 

 

 

 

 

 

Clock (C/C)

0.45

0.45

0.50

ns

tCLZ

tCHQX1

 

 

 

 

 

Rise to Low-Z [24, 25]

 

 

 

 

 

 

 

Clock (C/C)

–0.45

–0.45

–0.50

ns

DLL Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKC Var

tKC Var

Clock Phase Jitter

0.20

0.20

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

1024

1024

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

30

30

ns

Notes

21.When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timing of the frequency range in which it is being operated and outputs data with the output timings of that frequency range.

22.This part has a voltage regulator internally; tPOWER is the time that the power is supplied above VDD minimum initially before a read or write operation is initiated.

23.For D2 data signal on CY7C1910BV18 device, tSD is 0.5 ns for 200 MHz, and 250 MHz frequencies.

24.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady state voltage.

25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document #: 38-05619 Rev. *F

Page 23 of 29

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1310BV18Logic Block Diagram CY7C1910BV18 Logic Block Diagram CY7C1314BV18 Logic Block Diagram CY7C1312BV18CY7C1910BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1310BV18 2M xNC/72M NC/36M CY7C1312BV18 1M xWPS BWS CY7C1314BV18 512K xPin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Sram #1 Application ExampleProgrammable Impedance Echo ClocksComments Truth TableWrite Cycle Descriptions OperationInto the device. D359 remains unaltered Write cycle description table for CY7C1910BV18 followsWrite cycle description table for CY7C1314BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document # 38-05619 Rev. *F AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitDLL Timing Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Parameter Min MaxRead/Write/Deselect Sequence 26, 27 Switching WaveformsOrdering Information 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR Document HistorySYT VKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN