Cypress CY7C1292DV18 TAP AC Switching Characteristics Over the Operating Range13, Hold Times

Page 13

CY7C1292DV18

CY7C1294DV18

TAP AC Switching Characteristics Over the Operating Range[13, 14]

Parameter

Description

Min.

Max.

Unit

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH

20

 

ns

tTL

TCK Clock LOW

20

 

ns

Set-up Times

 

 

 

 

 

 

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

5

 

ns

tCS

Capture Set-up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Output Times

 

 

 

 

 

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

TAP Timing and Test Conditions[13]

 

 

0.9V

 

 

 

 

 

 

 

 

 

 

 

50

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDO

 

 

 

 

 

 

 

 

 

 

 

Z0 = 50

 

 

 

 

 

 

CL = 20 pF

 

 

0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tTH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

1.8V

0.9V

tTL

GND

(a)

Test Clock

TCK

Test Mode Select

TMS

Test Data-In

TDI

Test Data-Out

TDO

tTMSS

tTDIS

tTMSH

tTDIH

tTDOV

tTCYC

tTDOX

Notes:

13.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

14.tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.

Document #: 001-00350 Rev. *A

Page 13 of 23

[+] Feedback

Image 13
Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1294DV18 Logic Block Diagram CY7C1292DV18Doff TMS TDI Pin Configurations Ball Fbga 13 x 15 x 1.4 mm PinoutQ34 Pin Definitions Functional Overview DLL Write Cycle Descriptions CY7C1292DV18 2 Application Example1RPS WPS BWSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramTAP Timing and Test Conditions13 TAP AC Switching Characteristics Over the Operating Range13Parameter Description Min Max Unit Hold TimesScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower-up Waveforms Power-Up Sequence in QDR-II SramPower-Up Sequence DLL ConstraintsMaximum Ratings Electrical Characteristics Over the Operating Range12Operating Range CapacitanceAC Test Loads and Waveforms Thermal Resistance21Parameter Description Test Conditions Fbga Unit Test conditions follow standard test 28.51Set-up Times Switching Characteristics Over the Operating Range22Output Times DLL TimingRead/Write/Deselect Sequence Switching Waveforms27, 28Write Read Write NOPOrdering Information PIN 1 Corner Package DiagramDocument History ECN No Issue Date Orig. Description of ChangeREV SYT