Cypress CY7C1294DV18, CY7C1292DV18 manual Package Diagram, PIN 1 Corner

Page 22

CY7C1292DV18

CY7C1294DV18

Package Diagram

165 FBGA 13 x 15 x 1.40 MM BB165D/BW165D 165-ball FBGA (13 x 15 x 1.4 mm) (51-85180)

15.00±0.10

15.00±0.10

TOP VIEW

 

 

 

 

 

 

 

TOP VIEW

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

 

 

A

 

1

 

2

3

4

5

6

7

8

9

10

11

B

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP R

15.00±0.10

15.00±0.10

 

14.00

1.00

1.00

14.00

 

7.00

7.00

 

 

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

 

 

 

 

BOTTOM VIEWPIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

 

 

 

Ø0.50

-0Ø0.06

.25 M C A B

 

 

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

-0.06

 

 

 

11

10

9

8

7

6

5

Ø0.50

(165X)

 

4

3

2

1

 

 

 

 

 

 

 

 

 

 

 

 

+0.14

 

 

 

 

 

11

10

9

8

7

6

5

4

3

2

1A

BA

CB

DC

ED

FE

GF

HG

JH

KJ

LK

ML

NM

PN

RP

R

A

0.25 C

A

0.3600.25.3±0C .05

 

 

 

 

A

 

5.00

1.00

 

 

 

 

A

 

1.00

 

 

 

 

 

 

 

 

 

 

 

 

 

5.00

 

 

 

 

 

 

 

10.00

 

 

 

 

 

 

 

10.00

B

13.00±0.10

 

 

 

B

13.00±0.10

B

13.00±0.10

 

 

 

B

 

13.00±0.10

 

 

 

 

 

0.15(4X)

 

 

 

1.40 MAX.

 

 

 

0.15(4X)

 

 

 

 

1.40MAX.

 

NOTES :

 

 

0.53±0.05

0.15 C

0.15C

SOLDERNOTESPAD TYPE:

: NON-SOLDER MASK DEFINED (NSMD)

PACKAGESOLDERW IGHTPAD: 0TYPE.475g: NON-SOLDER MASK DEFINED (NSMD)

 

 

 

 

 

 

 

 

 

 

JEDEC REFERENCEPACKAGE WEIGHT: MO-216: 0./475gDESIGN 4.6C

PACKAGEJEDECODEREFERENCE: BB0AC : MO-216 / DESIGN 4.6C

 

 

SEATING PLANE

 

 

PACKAGE CODE : BB0AC

 

 

 

 

 

C

 

SEATING PLANE

 

 

51-85180-*A

0.36

 

 

C

0.35±0.06

0.35±0.06

 

 

 

 

51-85180-*A

 

 

 

 

 

 

 

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

Document #: 001-00350 Rev. *A

Page 22 of 23

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1294DV18 Logic Block Diagram CY7C1292DV18Doff TMS TDI Pin Configurations Ball Fbga 13 x 15 x 1.4 mm PinoutQ34 Pin Definitions Functional Overview DLL RPS WPS Application Example1Write Cycle Descriptions CY7C1292DV18 2 BWSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range13TAP Timing and Test Conditions13 Hold TimesInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower-Up Sequence Power-Up Sequence in QDR-II SramPower-up Waveforms DLL ConstraintsOperating Range Electrical Characteristics Over the Operating Range12Maximum Ratings CapacitanceParameter Description Test Conditions Fbga Unit Thermal Resistance21AC Test Loads and Waveforms Test conditions follow standard test 28.51Output Times Switching Characteristics Over the Operating Range22Set-up Times DLL TimingWrite Read Switching Waveforms27, 28Read/Write/Deselect Sequence Write NOPOrdering Information Package Diagram PIN 1 CornerREV ECN No Issue Date Orig. Description of ChangeDocument History SYT