Cypress CY7C1292DV18 Document History, Rev, ECN No Issue Date Orig. Description of Change, Syt

Page 23

CY7C1292DV18

CY7C1294DV18

Document History Page

Document Title: CY7C1292DV18/CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture

Document Number: 001-00350

REV.

ECN No.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

380737

See ECN

SYT

New data sheet

 

 

 

 

 

*A

485631

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Removed 300MHz Speed Bin.

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed C/C Pin Description in the features section and Pin Description.

 

 

 

 

Modified the ZQ Definition from Alternately, this pin can be connected directly

 

 

 

 

to VDD to Alternately, this pin can be connected directly to VDDQ.

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH,

 

 

 

 

tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table

 

 

 

 

Added power-up sequence details and waveforms.

 

 

 

 

Added foot notes #15 and 16 on page# 18.

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied

 

 

 

 

from –10°C to +85°C to –55°C to +125°C

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 13.

 

 

 

 

Modified the IDD and ISB values

 

 

 

 

Modified test condition in Footnote #20 on page# 19 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD.

 

 

 

 

Changed the Min. Value of tSC and tHC from 0.5ns to 0.35ns for 250 MHz and

 

 

 

 

0.6ns to 0.4ns for 200 MHz speed bins.

 

 

 

 

 

 

Changed the description of tSA from K Clock Rise to Clock

 

(K/K)

Rise.

 

 

 

 

Changed the description of tSC and tHC from Clock (K and K) Rise to K Clock

 

 

 

 

Rise.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated the Ordering Information Table.

Document #: 001-00350 Rev. *A

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Contents Selection Guide FeaturesConfigurations Functional DescriptionDoff Logic Block Diagram CY7C1292DV18Logic Block Diagram CY7C1294DV18 Q34 Pin Configurations Ball Fbga 13 x 15 x 1.4 mm PinoutTMS TDI Pin Definitions Functional Overview DLL BWS Application Example1Write Cycle Descriptions CY7C1292DV18 2 RPS WPSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramHold Times TAP AC Switching Characteristics Over the Operating Range13TAP Timing and Test Conditions13 Parameter Description Min Max UnitRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power-Up Sequence in QDR-II SramPower-up Waveforms Power-Up SequenceCapacitance Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeTest conditions follow standard test 28.51 Thermal Resistance21AC Test Loads and Waveforms Parameter Description Test Conditions Fbga UnitDLL Timing Switching Characteristics Over the Operating Range22Set-up Times Output TimesWrite NOP Switching Waveforms27, 28Read/Write/Deselect Sequence Write ReadOrdering Information PIN 1 Corner Package DiagramSYT ECN No Issue Date Orig. Description of ChangeDocument History REV
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