Cypress CY7C1292DV18 manual Pin Configurations Ball Fbga 13 x 15 x 1.4 mm Pinout, Tms Tdi, Q34

Page 3

CY7C1292DV18

CY7C1294DV18

Pin Configurations

165-ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1292DV18 (512K x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

NC/36M

1

NC/288M

NC/18M

NC/72M

CQ

CQ

WPS

BWS

K

RPS

B

NC

Q9

D9

A

NC

K

0

A

NC

NC

Q8

BWS

C

NC

NC

D10

VSS

A

A

A

VSS

NC

Q7

D8

D

NC

D11

Q10

VSS

VSS

VSS

VSS

VSS

NC

NC

D7

E

NC

NC

Q11

VDDQ

VSS

VSS

VSS

VDDQ

NC

D6

Q6

F

NC

Q12

D12

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

Q5

G

NC

D13

Q13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

D14

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q4

D4

K

NC

NC

Q14

VDDQ

VDD

VSS

VDD

VDDQ

NC

D3

Q3

L

NC

Q15

D15

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q2

M

NC

NC

D16

VSS

VSS

VSS

VSS

VSS

NC

Q1

D2

N

NC

D17

Q16

VSS

A

A

A

VSS

NC

NC

D1

P

NC

NC

Q17

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1294DV18 (256K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/288M

NC/72M

2

1

NC/36M

NC/144M

CQ

CQ

WPS

BWS

K

BWS

RPS

B

Q27

Q18

D18

A

3

K

0

A

D17

Q17

Q8

BWS

BWS

C

D27

Q28

D19

VSS

A

NC/18M

A

VSS

D16

Q7

D8

D

D28

D20

Q19

VSS

VSS

VSS

VSS

VSS

Q16

D15

D7

E

Q29

D29

Q20

VDDQ

VSS

VSS

VSS

VDDQ

Q15

D6

Q6

F

Q30

Q21

D21

VDDQ

VDD

VSS

VDD

VDDQ

D14

Q14

Q5

G

D30

D22

Q22

VDDQ

VDD

VSS

VDD

VDDQ

Q13

D13

D5

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

D31

Q31

D23

VDDQ

VDD

VSS

VDD

VDDQ

D12

Q4

D4

K

Q32

D32

Q23

VDDQ

VDD

VSS

VDD

VDDQ

Q12

D3

Q3

L

Q33

Q24

D24

VDDQ

VSS

VSS

VSS

VDDQ

D11

Q11

Q2

M

D33

Q34

D25

VSS

VSS

VSS

VSS

VSS

D10

Q1

D2

N

D34

D26

Q25

VSS

A

A

A

VSS

Q10

D9

D1

P

Q35

D35

Q26

A

A

C

A

A

Q9

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document #: 001-00350 Rev. *A

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1292DV18 Logic Block Diagram CY7C1294DV18Doff Pin Configurations Ball Fbga 13 x 15 x 1.4 mm Pinout TMS TDIQ34 Pin Definitions Functional Overview DLL BWS Application Example1Write Cycle Descriptions CY7C1292DV18 2 RPS WPSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram9Parameter Description Test Conditions Min Max Unit TAP Controller Block DiagramHold Times TAP AC Switching Characteristics Over the Operating Range13TAP Timing and Test Conditions13 Parameter Description Min Max UnitRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power-Up Sequence in QDR-II SramPower-up Waveforms Power-Up SequenceCapacitance Electrical Characteristics Over the Operating Range12Maximum Ratings Operating RangeTest conditions follow standard test 28.51 Thermal Resistance21AC Test Loads and Waveforms Parameter Description Test Conditions Fbga UnitDLL Timing Switching Characteristics Over the Operating Range22Set-up Times Output TimesWrite NOP Switching Waveforms27, 28Read/Write/Deselect Sequence Write ReadOrdering Information PIN 1 Corner Package DiagramSYT ECN No Issue Date Orig. Description of ChangeDocument History REV