Cypress CY7C1294DV18, CY7C1292DV18 manual Thermal Resistance21, AC Test Loads and Waveforms

Page 18

CY7C1292DV18

CY7C1294DV18

Thermal Resistance[21]

Parameter

Description

Test Conditions

165 FBGA

Unit

ΘJA

Thermal Resistance (Junction to Ambient)

Test conditions follow standard test

28.51

°C/W

 

 

methods and procedures for measuring

 

 

ΘJC

Thermal Resistance (Junction to Case)

5.91

°C/W

thermal impedance, per EIA/JESD51.

AC Test Loads and Waveforms

VREF = 0.75V

VREF

 

 

 

 

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

Z0 = 50Ω

 

 

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

 

 

 

 

 

 

 

 

 

 

 

ZQ

RQ =

250Ω

(a)

Note:

RL = 50Ω

VREF = 0.75V

VREF

 

 

 

0.75V

 

 

 

R = 50Ω

[22]

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

 

 

 

 

 

 

1.25V

 

 

 

 

 

 

 

 

 

 

Device

 

 

 

 

 

 

 

 

 

5 pF 0.25V

 

 

 

0.75V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Under

ZQ

 

 

 

 

 

 

 

 

 

Slew Rate = 2 V/ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Test

 

 

RQ =

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

250Ω

(b)

22.Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.

Document #: 001-00350 Rev. *A

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1292DV18 Logic Block Diagram CY7C1294DV18Doff Pin Configurations Ball Fbga 13 x 15 x 1.4 mm Pinout TMS TDIQ34 Pin Definitions Functional Overview DLL RPS WPS Application Example1Write Cycle Descriptions CY7C1292DV18 2 BWSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range13TAP Timing and Test Conditions13 Hold TimesInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower-Up Sequence Power-Up Sequence in QDR-II SramPower-up Waveforms DLL ConstraintsOperating Range Electrical Characteristics Over the Operating Range12Maximum Ratings CapacitanceParameter Description Test Conditions Fbga Unit Thermal Resistance21AC Test Loads and Waveforms Test conditions follow standard test 28.51Output Times Switching Characteristics Over the Operating Range22Set-up Times DLL TimingWrite Read Switching Waveforms27, 28Read/Write/Deselect Sequence Write NOPOrdering Information Package Diagram PIN 1 CornerREV ECN No Issue Date Orig. Description of ChangeDocument History SYT
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