Cypress CY7C1294DV18 manual Switching Waveforms27, 28, Read/Write/Deselect Sequence, Write Read

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CY7C1292DV18

CY7C1294DV18

Switching Waveforms[27, 28, 29]

Read/Write/Deselect Sequence

READ

WRITE

READ

WRITE

READ

WRITE

NOP

1

2

3

4

5

6

7

WRITE NOP

8 9 10

K

tKH

K

RPS

WPS

A

A0

tSA

 

tKL

 

 

 

tCYC

 

 

tKHKH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSC tHC

A2

A3

tSA tHA

A6

D D10

D11

 

D30

D50

D51

 

 

 

 

tSD

 

tSD

tHD

Q

 

 

 

Q00

Q01

Q20

 

 

 

tCLZ

 

tCQDOH

 

 

 

 

 

tDOH

 

 

tKHCH

tKL

tCO

 

 

 

CtKH

tKHCH

tKHKH

 

tCYC

 

 

 

 

 

 

 

 

C

tCCQO

tCQOH

CQ

tCCQO

tCQOH

CQ

D61

Q21 Q40

tCQD

CARE

Q41

tCHZ

UNDEFINED

Notes:

27.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1.

28.Output are disabled (High-Z) one clock cycle after a NOP.

29.In this example, if address A2 = A1,then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document #: 001-00350 Rev. *A

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1292DV18Logic Block Diagram CY7C1294DV18 Q34 Pin Configurations Ball Fbga 13 x 15 x 1.4 mm PinoutTMS TDI Pin Definitions Functional Overview DLL Application Example1 Write Cycle Descriptions CY7C1292DV18 2RPS WPS BWSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitTAP AC Switching Characteristics Over the Operating Range13 TAP Timing and Test Conditions13Parameter Description Min Max Unit Hold TimesIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower-Up Sequence in QDR-II Sram Power-up WaveformsPower-Up Sequence DLL ConstraintsElectrical Characteristics Over the Operating Range12 Maximum RatingsOperating Range CapacitanceThermal Resistance21 AC Test Loads and WaveformsParameter Description Test Conditions Fbga Unit Test conditions follow standard test 28.51Switching Characteristics Over the Operating Range22 Set-up TimesOutput Times DLL TimingSwitching Waveforms27, 28 Read/Write/Deselect SequenceWrite Read Write NOPOrdering Information Package Diagram PIN 1 CornerECN No Issue Date Orig. Description of Change Document HistoryREV SYT