Cypress CY7C1292DV18 manual Switching Characteristics Over the Operating Range22, Set-up Times

CY7C1292DV18

CY7C1294DV18

Switching Characteristics Over the Operating Range[22, 23]

Cypress

Consortium

250 MHz

200 MHz

167 MHz

Parameter

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Unit

t

t

V (Typical) to the first Access[24]

1

1

1

ms

POWER

KHKH

DD

tCYC

tKHKL

K Clock and C Clock Cycle Time

4.0

6.3

5.0

7.9

6.0

7.9

ns

tKH

tKLKH

1.6

–

2.0

–

2.4

–

ns

Input Clock (K/K

and C/C) HIGH

tKL

tKHKH

1.6

–

2.0

–

2.4

–

ns

Input Clock (K/K

and C/C) LOW

K Clock Rise to

Clock Rise and C to

Rise

tKHKH

tKHCH

K

C

1.8

–

2.2

–

2.7

–

ns

(rising edge to rising edge)

tKHCH

tKHKH

K/K

Clock Rise to C/C Clock Rise

0.0

1.8

0.0

2.2

0.0

2.7

ns

(rising edge to rising edge)

Set-up Times

tSA

tAVKH

Address Set-up to Clock (K/K)

Rise

0.35

–

0.4

–

0.5

–

ns

tSC

tIVKH

Control Set-up to K Clock Rise

0.35

–

0.4

–

0.5

–

ns

(RPS,

WPS)

Double Data Rate Control Set-up to Clock

tSCDDR

tIVKH

(K/K) Rise (BWS0, BWS1, BWS3, BWS4)

0.35

–

0.4

–

0.5

–

ns

tSD

tDVKH

D

Rise

0.35

–

0.4

–

0.5

–

ns

Set-up to Clock (K/K)

[X:0]

Hold Times

tHA

tKHAX

Address Hold after Clock (K/K)

Rise

0.35

–

0.4

–

0.5

–

ns

tHC

tKHIX

Control Hold after K Clock Rise

0.35

–

0.4

–

0.5

–

ns

(RPS,

WPS)

Double Data Rate Control Hold after Clock

tHCDDR

tKHIX

(K/K) Rise (BWS0, BWS1, BWS3, BWS4)

0.35

–

0.4

–

0.5

–

ns

tHD

tKHDX

D

Rise

0.35

–

0.4

–

0.5

–

ns

Hold after Clock (K/K)

[X:0]

Output Times

tCO

tCHQV

C/C

Clock Rise (or K/K

in Single Clock Mode)

–

0.45

–

0.45

–

0.50

ns

to Data Valid

Clock Rise

tDOH

tCHQX

Data Output Hold after Output C/C

–0.45

–

-0.45

–

-0.50

–

ns

(Active to Active)

tCCQO

tCHCQV

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.50

ns

C/C

tCQOH

tCHCQX

Clock Rise

–0.45

–

–0.45

–

–0.50

–

ns

Echo Clock Hold after C/C

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.30

–

0.35

–

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.30

–

–0.35

–

–0.40

–

ns

Rise to High-Z

Clock (C/C)

tCHZ

tCHQZ

(Active to High-Z)[25,26]

–

0.45

–

0.45

–

0.50

ns

tCLZ

tCHQX1

Rise to Low-Z[25,26]

–0.45

–

–0.45

–

–0.50

–

ns

Clock (C/C)

DLL Timing

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

–

30

–

30

–

ns

Notes:

23.All devices can operate at clock frequencies as low as 119 MHz. When a part with a maximum frequency above 133 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range.

24.This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.

25.tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

26.At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document #: 001-00350 Rev. *A Page 19 of 23

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