Cypress CY7C1294DV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1292DV18

 

 

 

 

 

 

 

 

 

 

 

CY7C1294DV18

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Value

 

 

 

Instruction Field

 

 

CY7C1292DV18

 

 

CY7C1294DV18

 

Description

 

 

 

 

 

 

 

 

 

 

Revision Number (31:29)

 

000

 

 

000

 

Version number.

 

 

 

 

 

 

 

 

 

 

Cypress Device ID (28:12)

 

11010011010010110

 

11010011010100110

 

Defines the type of SRAM.

 

 

 

 

 

 

 

 

 

 

Cypress JEDEC ID (11:1)

 

00000110100

 

 

00000110100

 

Unique identification of SRAM vendor.

 

 

 

 

 

 

 

 

 

 

ID Register Presence (0)

 

1

 

 

1

 

Indicates the presence of an ID register.

 

 

 

 

 

 

 

 

 

 

 

Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

Bit Size

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bypass

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Cells

 

107

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Codes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

Code

 

 

 

 

Description

 

 

 

EXTEST

000

Captures the Input/Output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between

 

 

 

 

 

 

TDI and TDO. This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the Input/Output contents. Places the boundary scan register

 

 

 

 

 

 

between TDI and TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the Input/Output ring contents. Places the boundary scan register

 

 

 

 

 

 

between TDI and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not

 

 

 

 

 

 

affect SRAM operation.

 

 

 

Document #: 001-00350 Rev. *A

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1292DV18Logic Block Diagram CY7C1294DV18 Q34 Pin Configurations Ball Fbga 13 x 15 x 1.4 mm PinoutTMS TDI Pin Definitions Functional Overview DLL RPS WPS Application Example1Write Cycle Descriptions CY7C1292DV18 2 BWSWrite Cycle Descriptions CY7C1294DV18 2 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram9 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit TAP AC Switching Characteristics Over the Operating Range13TAP Timing and Test Conditions13 Hold TimesInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower-Up Sequence Power-Up Sequence in QDR-II SramPower-up Waveforms DLL ConstraintsOperating Range Electrical Characteristics Over the Operating Range12Maximum Ratings CapacitanceParameter Description Test Conditions Fbga Unit Thermal Resistance21AC Test Loads and Waveforms Test conditions follow standard test 28.51Output Times Switching Characteristics Over the Operating Range22Set-up Times DLL TimingWrite Read Switching Waveforms27, 28Read/Write/Deselect Sequence Write NOPOrdering Information Package Diagram PIN 1 CornerREV ECN No Issue Date Orig. Description of ChangeDocument History SYT