Cypress CY7C1410AV18 Document History, REV ECN no Submission ORIG. Description of Change Date

Page 28

CY7C1410AV18, CY7C1425AV18

CY7C1412AV18, CY7C1414AV18

Document History Page

Document Title: CY7C1410AV18/CY7C1425AV18/CY7C1412AV18/CY7C1414AV18, 36-Mbit QDR™-II SRAM 2-Word Burst

Architecture

Document Number: 38-05615

REV.

ECN NO.

SUBMISSION

ORIG. OF

DESCRIPTION OF CHANGE

DATE

CHANGE

 

 

 

 

 

**

247331

See ECN

SYT

New Data Sheet

 

 

 

 

 

*A

326519

See ECN

SYT

Removed CY7C1425AV18 from the title

 

 

 

 

Included 300 MHz Speed grade

 

 

 

 

Replaced TBDs with their respective values for IDD and ISB1

 

 

 

 

Added Industrial temperature grade

 

 

 

 

Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W and

 

 

 

 

ΘJC = 3.2°C/W

 

 

 

 

Replaced TBDs in the Capacitance Table to their respective values for the

 

 

 

 

165 FBGA Package

 

 

 

 

Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS

 

 

 

 

TRI-STATE on Page 16

 

 

 

 

Added Pb-free Product Information

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs according

 

 

 

 

to availability

*B

413953

See ECN

NXR

Converted from preliminary to final.

 

 

 

 

Added CY7C1425AV18 part number to title.

 

 

 

 

Removed 300-MHz speed Bin.

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

 

 

 

 

North First Street” to “198 Champion Court”

 

 

 

 

Changed C, C Description in Feature Section and Pin Description.

 

 

 

 

Added Power up sequence and Wave form on page# 19

 

 

 

 

Added foot notes # 13, 14, 15 on page# 19

 

 

 

 

Replaced Three-state with Tri-state.

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current

 

 

 

 

on page# 20

 

 

 

 

Modified the IDD and ISB values.

 

 

 

 

Modified test condition in Footnote # 20 on page# 20 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated Ordering Information Table.

*C

468029

See ECN

NXR

Modified the ZQ Definition from Alternately, this pin can be connected directly to

 

 

 

 

VDD to Alternately, this pin can be connected directly to VDDQ.

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH,

 

 

 

 

tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power Up waveform

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied from

 

 

 

 

–10°C to +85°C to –55°C to +125°C

 

 

 

 

Added additional notes in the AC parameter section

 

 

 

 

Changed the tSC and tHC value for 250 MHz from 0.5 ns to 0.35 ns,

 

 

 

 

for 200 MHz from 0.6 ns to 0.4 ns, and for 167 MHz from 0.7 ns to 0.5 ns.

 

 

 

 

Modified AC Switching Waveform.

 

 

 

 

Corrected the typo In the AC Switching Characteristics Table.

 

 

 

 

Updated the Ordering Information Table.

*D

1274725

See ECN

VKN/AESA

Modified footnote# 30

 

 

 

 

 

Document #: 38-05615 Rev. *E

Page 28 of 29

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1425AV18 Logic Block Diagram CY7C1410AV18Doff Logic Block Diagram CY7C1412AV18 Logic Block Diagram CY7C1414AV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1410AV18 4M x CY7C1425AV18 4M xWPS BWS CY7C1412AV18 2M xCY7C1414AV18 1M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks Sram #1Truth Table Write Cycle DescriptionsRPS WPS BWS0 BWS1BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Cypress Consortium Description 250 MHz 200 MHz 167 MHz UnitParameter Min Max DLL TimingWrite Read Switching WaveformsWrite NOP Ordering Information 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History REV ECN no Submission ORIG. Description of Change DateSYT NXRWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationUSB