Cypress CY7C1412AV18, CY7C1410AV18, CY7C1425AV18 manual Package Diagram, Ball Fbga 15 x 17 x 1.4 mm

Page 27

CY7C1410AV18, CY7C1425AV18

CY7C1412AV18, CY7C1414AV18

Package Diagram

Figure 6. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85195

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

 

BOTTOM VIEW

 

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.25 M C A B

 

 

 

 

 

 

 

 

Ø0.50

 

+0.14

 

 

 

 

 

 

 

 

 

 

(165X)

 

 

 

 

 

 

 

 

 

 

 

-0.06

 

 

 

 

11

10

9

8

7

6

5

4

3

2

1

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

B

 

1.00

 

 

 

 

 

 

 

 

 

C

 

 

 

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

 

 

F

17.00±0.10

14.00

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

 

 

H

 

 

 

 

 

 

 

 

 

 

 

J

 

 

 

 

 

 

 

 

 

 

 

K

 

7.00

 

 

 

 

 

 

 

 

 

L

 

 

 

 

 

 

 

 

 

 

M

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

N

 

 

 

 

 

 

 

 

 

 

 

P

 

 

 

 

 

 

 

 

 

 

 

R

A

 

 

 

 

 

 

 

1.00

 

 

 

 

 

5.00

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10.00

 

 

 

 

 

 

B

 

 

15.00±0.10

 

 

 

 

 

0.15(4X)

0.25 C

0.53±0.05

C 0.36

0.35±0.06

0.15 C

SEATING PLANE

 

 

1.40 MAX.

NOTES :

SOLDER PAD TYPE : NON SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.65g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C

PACKAGE CODE : BB0AD

51-85195-*A

Document #: 38-05615 Rev. *E

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1410AV18 Logic Block Diagram CY7C1425AV18Doff Logic Block Diagram CY7C1414AV18 Logic Block Diagram CY7C1412AV18CY7C1425AV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1410AV18 4M xCY7C1412AV18 2M x WPS BWSCY7C1414AV18 1M x Pin Name Pin Description Pin DefinitionsTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview Sram #1 Application ExampleProgrammable Impedance Echo ClocksBWS0 BWS1 Truth TableWrite Cycle Descriptions RPS WPSBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitDLL Timing Switching CharacteristicsCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Parameter Min Max Switching Waveforms Write Read Write NOP Ordering Information 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramNXR Document HistoryREV ECN no Submission ORIG. Description of Change Date SYTSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsUSB
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