Cypress CY7C1425AV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1410AV18, CY7C1425AV18

CY7C1412AV18, CY7C1414AV18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1410AV18	CY7C1425AV18	CY7C1412AV18	CY7C1414AV18	Description
		CY7C1410AV18	CY7C1425AV18	CY7C1412AV18	CY7C1414AV18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010011010000111	11010011010001111	11010011010010111	11010011010100111	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Allows unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document #: 38-05615 Rev. *E

Page 17 of 29

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1410AV18Logic Block Diagram CY7C1425AV18 Logic Block Diagram CY7C1414AV18 Logic Block Diagram CY7C1412AV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1410AV18 4M x CY7C1425AV18 4M xCY7C1414AV18 1M x CY7C1412AV18 2M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Programmable Impedance Application ExampleEcho Clocks Sram #1Write Cycle Descriptions Truth TableRPS WPS BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitCypress Consortium Description 250 MHz 200 MHz 167 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingWrite NOP Switching WaveformsWrite Read Ordering Information 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN no Submission ORIG. Description of Change Date Document HistorySYT NXRUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions