Cypress CY7C1426BV18, CY7C1411BV18, CY7C1413BV18, CY7C1415BV18 manual TAP Controller State Diagram

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CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

TAP Controller State Diagram

The state diagram for the TAP controller follows. [11]

1

0

TEST-LOGIC RESET

0

TEST-LOGIC/ IDLE

1

 

1

1

SELECT

SELECT

 

DR-SCAN

 

IR-SCAN

 

0

 

0

 

1

 

1

CAPTURE-DR

 

CAPTURE-IR

 

0

 

0

 

SHIFT-DR

0

SHIFT-IR

0

1

 

1

 

EXIT1-DR

1

EXIT1-IR

1

 

 

0

 

0

 

PAUSE-DR

0

PAUSE-IR

0

1

 

1

 

0

 

0

 

EXIT2-DR

 

EXIT2-IR

 

1

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

 

1

 

0

 

0

 

Note

11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

Document Number: 001-07037 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1411BV18Logic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1413BV18 Logic Block Diagram CY7C1415BV18CY7C1411BV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1426BV18 4M xCY7C1415BV18 1M x CY7C1413BV18 2M xWPS BWS Pin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo ClocksOperation Truth TableWrite Cycle Descriptions CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitLOW Switching CharacteristicsHigh RPS, WPSStatic to DLL Reset DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions