Cypress CY7C1411BV18, CY7C1413BV18, CY7C1426BV18, CY7C1415BV18 manual 167

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CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
167	CY7C1411BV18-167BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1426BV18-167BZC

	CY7C1413BV18-167BZC

	CY7C1415BV18-167BZC

	CY7C1411BV18-167BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1426BV18-167BZXC

	CY7C1413BV18-167BZXC

	CY7C1415BV18-167BZXC

	CY7C1411BV18-167BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1426BV18-167BZI

	CY7C1413BV18-167BZI

	CY7C1415BV18-167BZI

	CY7C1411BV18-167BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1426BV18-167BZXI

	CY7C1413BV18-167BZXI

	CY7C1415BV18-167BZXI

Document Number: 001-07037 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1411BV18Doff Logic Block Diagram CY7C1413BV18 Logic Block Diagram CY7C1415BV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1411BV18 4M x CY7C1426BV18 4M xWPS BWS CY7C1413BV18 2M xCY7C1415BV18 1M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Write Cycle DescriptionsOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW RPS, WPSStatic to DLL Reset DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions