Cypress CY7C1413BV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 17

CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Identification Register Definitions

Instruction Field

Value

CY7C1411BV18

CY7C1426BV18

CY7C1413BV18

CY7C1415BV18

Description

Revision Number

000

000

000

000

Version number.

(31:29)

 

 

 

 

 

 

 

 

 

 

 

Cypress Device ID

11010011011000111

11010011011001111

11010011011010111

11010011011100111

Defines the type of

(28:12)

 

 

 

 

SRAM.

Cypress JEDEC ID

00000110100

00000110100

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

identification of

 

 

 

 

 

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

 

 

 

 

presence of an ID

 

 

 

 

 

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

Bypass

ID

Boundary Scan

3

1

32

109

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document Number: 001-07037 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1411BV18Logic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1415BV18 Logic Block Diagram CY7C1413BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1411BV18 4M x CY7C1426BV18 4M xCY7C1415BV18 1M x CY7C1413BV18 2M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksWrite Cycle Descriptions Truth TableOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW RPS, WPSDLL Timing Static to DLL ResetRead/Write/Deselect Sequence 29, 30 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information