Cypress CY7C1413BV18, CY7C1411BV18 manual Switching Waveforms, Read/Write/Deselect Sequence 29, 30

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CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Switching Waveforms

Figure 5. Read/Write/Deselect Sequence [29, 30, 31]

NOP	READ	WRITE	READ	WRITE	NOP	7
1	2	3	4	5	6	7

K

K RPS

WPS

t KH

tKL t CYC t KHKH

t SC tHC

t SC t HC

A	A0	A1	A2
	tSA	tHA

tSD

D

Q

Q00

A3
tHD	t HD
tSD
D12			D32	D33
Q02	Q20	Q21	Q22
tCO	tCQDOH			t CHZ

t KHCH

t KHCH t CLZ

tDOH										tCQD

C

C

CQ

CQ

t CQH

t CYC	t KHKH
	t	CQOH	t CCQO
		CQOH
t CQHCQH			t CCQO
			t CQOH

t KH

tKL

DON’T CARE

UNDEFINED

Notes

29.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0+1.

30.Outputs are disabled (High-Z) one clock cycle after a NOP.

31.In this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, and Q23 = D13. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-07037 Rev. *D

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1411BV18Doff Logic Block Diagram CY7C1415BV18 Logic Block Diagram CY7C1413BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1411BV18 4M x CY7C1426BV18 4M xWPS BWS CY7C1413BV18 2M xCY7C1415BV18 1M x Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksWrite Cycle Descriptions Truth TableOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW RPS, WPSDLL Timing Static to DLL ResetRead/Write/Deselect Sequence 29, 30 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information