Cypress CY7C1411BV18, CY7C1413BV18 manual Maximum Ratings, DC Electrical Characteristics

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CY7C1411BV18, CY7C1426BV18 CY7C1413BV18, CY7C1415BV18

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND

–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND

–0.5V to +VDD

DC Applied to Outputs in High-Z

–0.5V to VDDQ + 0.3V

DC Input Voltage [13]

–0.5V to V + 0.3V

 

 

DD

Current into Outputs (LOW)

 

20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)..

> 2001V

Latch-up Current

...................................................

 

> 200 mA

Operating Range

 

 

 

 

 

 

 

 

 

Ambient

VDD [17]

VDDQ [17]

Range

 

Temperature (TA)

Commercial

 

0°C to +70°C

1.8 ± 0.1V

1.4V to

 

 

 

 

VDD

Industrial

 

–40°C to +85°C

 

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VDD

Power Supply Voltage

 

 

 

1.7

1.8

1.9

V

VDDQ

IO Supply Voltage

 

 

 

1.4

1.5

VDD

V

VOH

Output HIGH Voltage

Note 18

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOL

Output LOW Voltage

Note 19

 

 

VDDQ/2 – 0.12

 

VDDQ/2 + 0.12

V

VOH(LOW)

Output HIGH Voltage

IOH = 0.1 mA, Nominal Impedance

 

VDDQ – 0.2

 

VDDQ

V

VOL(LOW)

Output LOW Voltage

IOL = 0.1 mA, Nominal Impedance

 

VSS

 

0.2

V

VIH

Input HIGH Voltage

 

 

 

VREF + 0.1

 

VDDQ + 0.15

V

VIL

Input LOW Voltage

 

 

 

–0.3

 

VREF – 0.1

V

IX

Input Leakage Current

GND VI VDDQ

 

 

5

 

5

μA

IOZ

Output Leakage Current

GND VI VDDQ, Output Disabled

 

5

 

5

μA

VREF

Input Reference Voltage [20]

Typical Value = 0.75V

 

 

0.68

0.75

0.95

V

IDD [21]

VDD Operating Supply

VDD = Max,

300MHz

(x8)

 

 

885

mA

 

 

IOUT = 0 mA,

 

 

 

 

 

 

 

 

 

(x9)

 

 

900

 

 

 

f = fMAX = 1/tCYC

 

 

 

 

 

 

 

 

 

(x18)

 

 

940

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

1040

 

 

 

 

 

 

 

 

 

 

 

 

 

278MHz

(x8)

 

 

815

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

830

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

865

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

950

 

 

 

 

 

 

 

 

 

 

 

 

 

250MHz

(x8)

 

 

745

mA

 

 

 

 

 

 

 

 

 

 

 

 

 

(x9)

 

 

760

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x18)

 

 

790

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(x36)

 

 

870

 

 

 

 

 

 

 

 

 

 

Notes

17.Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

18.Output are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

19.Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

20.VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

21.The operation current is calculated with 50% read cycle and 50% write cycle.

Document Number: 001-07037 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1411BV18Logic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1413BV18 Logic Block Diagram CY7C1415BV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1411BV18 4M x CY7C1426BV18 4M xCY7C1415BV18 1M x CY7C1413BV18 2M xWPS BWS Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Write Cycle DescriptionsOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW RPS, WPSStatic to DLL Reset DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions