Cypress CY7C1426BV18, CY7C1411BV18, CY7C1413BV18 manual Sales, Solutions, and Legal Information

Page 30

CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Document History Page

Document Title: CY7C1411BV18/CY7C1426BV18/CY7C1413BV18/CY7C1415BV18, 36-Mbit QDR™-II SRAM 4-Word

Burst Architecture

Document Number: 001-07037

REV.

ECN NO.

SUBMISSION

ORIG. OF

DESCRIPTION OF CHANGE

DATE

CHANGE

 

 

 

 

 

**

433267

See ECN

NXR

New Data Sheet

 

 

 

 

 

*A

462004

See ECN

NXR

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH,

 

 

 

 

tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power Up waveform

*B

850381

See ECN

VKN

Minor change: Moved datasheet to the web

 

 

 

 

 

*C

1523289

See ECN

VKN/AESA

Converted from preliminary to final, Updated Logic Block diagram, Updated

 

 

 

 

IDD/ISB specs, Changed DLL minimum operating frequency from 80MHz to

 

 

 

 

120MHz, Changed tCYC max spec to 8.4ns, Modified footnotes 22 and 30

*D

2478647

See ECN

VKN/AESA

Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to

 

 

 

 

“–55°C to +125°C” in the “Maximum Ratings “ on page 20, Updated Power-up

 

 

 

 

sequence waveform and it’s description, Updated IDD/ISB specs, Added footnote

 

 

 

 

#21 related to IDD, Changed JTAG ID [31:29] from 001 to 000.

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© Cypress Semiconductor Corporation, 2006-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document Number: 001-07037 Rev. *D

Revised June 16, 2008

Page 30 of 30

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1411BV18 Logic Block Diagram CY7C1426BV18Doff Logic Block Diagram CY7C1413BV18 Logic Block Diagram CY7C1415BV18CY7C1411BV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1426BV18 4M xCY7C1413BV18 2M x WPS BWSCY7C1415BV18 1M x Pin Definitions Pin Name Pin DescriptionReferenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo ClocksOperation Truth TableWrite Cycle Descriptions CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitLOW Switching CharacteristicsHigh RPS, WPSStatic to DLL Reset DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30Ordering Information 250 167 Package Diagram Ball Fbga 15 x 17 x 1.4 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions