Cypress CY7C1413BV18, CY7C1411BV18, CY7C1426BV18 manual Package Diagram, Ball Fbga 15 x 17 x 1.4 mm

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CY7C1411BV18, CY7C1426BV18

CY7C1413BV18, CY7C1415BV18

Package Diagram

Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195

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Document Number: 001-07037 Rev. *D

Page 29 of 30

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Contents Configurations FeaturesFunctional Description Selection GuideDoff Logic Block Diagram CY7C1411BV18Logic Block Diagram CY7C1426BV18 Logic Block Diagram CY7C1415BV18 Logic Block Diagram CY7C1413BV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1411BV18 4M x CY7C1426BV18 4M xCY7C1415BV18 1M x CY7C1413BV18 2M xWPS BWS Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksWrite Cycle Descriptions Truth TableOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW RPS, WPSDLL Timing Static to DLL ResetRead/Write/Deselect Sequence 29, 30 Switching WaveformsOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information