Cypress CY7C1387D Identification Register Definitions, Scan Register Sizes, Identification Codes

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CY7C1386D, CY7C1386F

 

 

 

 

 

 

CY7C1387D, CY7C1387F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register Definitions

 

 

 

 

 

 

 

 

 

 

 

 

Instruction Field

CY7C1386D/CY7C1386F

CY7C1387D/CY7C1387F

 

Description

(512K × 36)

(1M × 18)

 

 

 

 

 

 

 

 

Revision Number (31:29)

000

 

000

 

Describes the version number

 

 

 

 

 

 

 

Device Depth (28:24) [13]

01011

 

01011

 

Reserved for internal use.

Device Width (23:18) 119-BGA

101110

 

101110

 

Defines the memory type and

 

 

 

 

 

 

 

architecture.

Device Width (23:18) 165-FBGA

000110

 

000110

 

Defines the memory type and

 

 

 

 

 

 

 

architecture.

Cypress Device ID (17:12)

100101

 

010101

 

Defines the width and density.

 

 

 

 

 

 

 

Cypress JEDEC ID Code (11:1)

00000110100

00000110100

 

Allows unique identification of SRAM

 

 

 

 

 

 

 

vendor.

ID Register Presence Indicator (0)

1

 

1

 

Indicates the presence of an ID

 

 

 

 

 

 

 

register.

Scan Register Sizes

 

 

 

 

 

 

 

 

 

 

 

 

Register Name

 

Bit Size (x18)

 

 

Bit Size (x36)

 

 

 

 

 

 

 

Instruction

 

 

3

 

 

3

 

 

 

 

 

 

 

Bypass

 

 

1

 

 

1

 

 

 

 

 

 

 

ID

 

 

32

 

 

32

 

 

 

 

 

 

Boundary Scan Order (119-ball BGA package)

 

85

 

 

85

 

 

 

 

 

 

Boundary Scan Order (165-ball FBGA package)

 

89

 

 

89

 

 

 

 

 

 

 

 

 

Identification Codes

Instruction

Code

Description

 

 

 

EXTEST

000

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM outputs to High-Z state.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and

 

 

TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

 

 

Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use. This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOA

100

Captures IO ring contents. Places the boundary scan register between TDI and TDO.

D

 

Does not affect SRAM operation.

RESERVED

101

Do Not Use. This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use. This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operations.

Note

13. Bit #24 is 1 in the register definitions for both 2.5V and 3.3V versions of this device.

Document Number: 38-05545 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesSelection Guide 250 MHz 200 MHz 167 MHz UnitLogic Block Diagram CY7C1387D/CY7C1387F 3 1M x Logic Block Diagram CY7C1386D/CY7C1386F 3 512K xPin Configurations Pin Tqfp Pinout 3 Chip Enables CY7C1386D 512K XCY7C1387D 1M x Pin Configurations Ball BGA Pinout 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Byte write select inputs, active LOW. Qualified with Power supply inputs to the core of the devicePin Definitions Name DescriptionFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Add. Used Truth Table for Read/Write 6 Function CY7C1386D/CY7C1386FFunction CY7C1387D/CY7C1387F TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsGND VIN Vddq 3V TAP AC Test Conditions5V TAP AC Test Conditions 3V TAP AC Output Load EquivalentRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Identification CodesBall BGA Boundary Scan Order 14 Bit # Ball IDInternal G10 F10 Internal A10 B10M11 M10Range Ambient Electrical CharacteristicsMaximum Ratings Operating RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms Description 250 200 167 Unit Parameter Min Switching Characteristics Over the Operating Range 20Read Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Date Orig. Description of Change Document HistoryDocument Number
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