Cypress CY7C1387F, CY7C1386F, CY7C1386D, CY7C1387D TAP Timing, TAP AC Switching Characteristics

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CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F

the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell will latch into the preload

register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is preset HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state.

Reserved

These instructions are not implemented but are reserved for future use. Do not use these instructions.

TAP Timing

1

2

Test Clock

 

(TCK)

tTH

 

tTMSS

tTMSH

Test Mode Select

 

(TMS)

 

tTDIS

tTDIH

Test Data-In

 

(TDI)

 

Test Data-Out

 

(TDO)

 

3

tTL tCYC

456

tTDOV

tTDOX

DON’T CARE

UNDEFINED

TAP AC Switching Characteristics

Over the Operating Range [10, 11]

Parameter

Description

Min

Max

Unit

Clock

 

 

 

 

 

 

 

 

 

tTCYC

TCK Clock Cycle Time

50

 

ns

tTF

TCK Clock Frequency

 

20

MHz

tTH

TCK Clock HIGH time

20

 

ns

tTL

TCK Clock LOW time

20

 

ns

Output Times

 

 

 

 

tTDOV

TCK Clock LOW to TDO Valid

 

10

ns

tTDOX

TCK Clock LOW to TDO Invalid

0

 

ns

Set-up Times

 

 

 

 

tTMSS

TMS Set-up to TCK Clock Rise

5

 

ns

tTDIS

TDI Set-up to TCK Clock Rise

5

 

ns

tCS

Capture Set-up to TCK Rise

5

 

ns

Hold Times

 

 

 

 

 

 

 

 

 

tTMSH

TMS Hold after TCK Clock Rise

5

 

ns

tTDIH

TDI Hold after Clock Rise

5

 

ns

tCH

Capture Hold after Clock Rise

5

 

ns

Notes

10.tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

11.Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.

Document Number: 38-05545 Rev. *E

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Contents Selection Guide Features250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1387D/CY7C1387F 3 1M x Logic Block Diagram CY7C1386D/CY7C1386F 3 512K xCY7C1386D 512K X Pin Configurations Pin Tqfp Pinout 3 Chip EnablesCY7C1387D 1M x Pin Configurations Ball BGA Pinout 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Pin Definitions Power supply inputs to the core of the deviceName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Add. Used Function CY7C1386D/CY7C1386F Truth Table for Read/Write 6Function CY7C1387D/CY7C1387F TAP Controller Block Diagram TAP Controller State DiagramTAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching Characteristics5V TAP AC Test Conditions 3V TAP AC Test Conditions3V TAP AC Output Load Equivalent GND VIN VddqScan Register Sizes Identification Register DefinitionsIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14Internal M11 A10 B10M10 G10 F10 InternalMaximum Ratings Electrical CharacteristicsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms Description 250 200 167 Unit Parameter Min Switching Characteristics Over the Operating Range 20Read Cycle Timing Switching WaveformsAdsc Write Cycle Timing 26Read/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History Issue Date Orig. Description of ChangeDocument Number