Cypress CY7C1386F, CY7C1387F, CY7C1386D, CY7C1387D Pin Configurations Ball BGA Pinout 1 Chip Enable

Page 4

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Pin Configurations (continued)

119-Ball BGA Pinout (1 Chip Enable)

CY7C1386F (512K x 36)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQC

DQPC

VSS

NC

VSS

DQPB

DQB

E

DQC

DQC

VSS

1

VSS

DQB

DQB

CE

F

VDDQ

DQC

VSS

VSS

DQB

VDDQ

OE

G

DQC

DQC

C

B

DQB

DQB

BW

ADV

BW

H

DQC

DQC

VSS

VSS

DQB

DQB

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

DQD

DQD

VSS

CLK

VSS

DQA

DQA

L

DQD

DQD

D

NC

A

DQA

DQA

BW

BW

M

VDDQ

DQD

VSS

VSS

DQA

VDDQ

BWE

N

DQD

DQD

VSS

A1

VSS

DQA

DQA

P

DQD

DQPD

VSS

A0

VSS

DQPA

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC

NC/72M

A

A

A

NC/36M

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

CY7C1387F (1M x 18)

1

2

3

4

5

6

7

A

VDDQ

A

A

A

A

VDDQ

ADSP

B

NC/288M

A

A

A

A

NC/576M

ADSC

C

NC/144M

A

A

VDD

A

A

NC/1G

D

DQB

NC

VSS

NC

VSS

DQPA

NC

E

NC

DQB

VSS

1

VSS

NC

DQA

CE

F

VDDQ

NC

VSS

VSS

DQA

VDDQ

OE

G

NC

DQB

B

NC

NC

DQA

BW

ADV

H

DQB

NC

VSS

VSS

DQA

NC

GW

J

VDDQ

VDD

NC

VDD

NC

VDD

VDDQ

K

NC

DQB

VSS

CLK

VSS

NC

DQA

L

DQB

NC

NC

NC

A

DQA

NC

BW

M

VDDQ

DQB

VSS

VSS

NC

VDDQ

BWE

N

DQB

NC

VSS

A1

VSS

DQA

NC

P

NC

DQPB

VSS

A0

VSS

NC

DQA

R

NC

A

MODE

VDD

NC

A

NC

T

NC/72M

A

A

NC/36M

A

A

ZZ

U

VDDQ

TMS

TDI

TCK

TDO

NC

VDDQ

Document Number: 38-05545 Rev. *E

Page 4 of 30

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Contents Features Selection Guide250 MHz 200 MHz 167 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1386D/CY7C1386F 3 512K x Logic Block Diagram CY7C1387D/CY7C1387F 3 1M xCY7C1386D 512K X Pin Configurations Pin Tqfp Pinout 3 Chip EnablesCY7C1387D 1M x Pin Configurations Ball BGA Pinout 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Power supply inputs to the core of the device Pin DefinitionsName Description Byte write select inputs, active LOW. Qualified withFunctional Overview Linear Burst Address Table Mode = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics Operation Add. Used Function CY7C1386D/CY7C1386F Truth Table for Read/Write 6Function CY7C1387D/CY7C1387F TAP Controller State Diagram TAP Controller Block DiagramBypass Register TAP Instruction SetTAP AC Switching Characteristics TAP Timing3V TAP AC Test Conditions 5V TAP AC Test Conditions3V TAP AC Output Load Equivalent GND VIN VddqIdentification Register Definitions Scan Register SizesIdentification Codes Register Name Bit SizeBit # Ball ID Ball BGA Boundary Scan Order 14Internal A10 B10 M11M10 G10 F10 InternalElectrical Characteristics Maximum RatingsOperating Range Range AmbientThermal Resistance CapacitanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 20 Description 250 200 167 Unit Parameter MinSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Document History Issue Date Orig. Description of ChangeDocument Number