Cypress CY7C1386D manual Document History, Document Number, Issue Date Orig. Description of Change

Page 30

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document History Page

Document Title: CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F, 18-Mbit (512K x 36/1 Mbit x 18) Pipelined DCD Sync

SRAM

Document Number: 38-05545

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

 

 

 

 

**

254550

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 225Mhz Speed Bin

 

 

 

 

Added Pb-free information for 100-pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

Packages.

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Added description on EXTEST Output Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000110 to 101110

 

 

 

 

Added separate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and

 

 

 

 

4.08 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for BGA Package from 45 and 7 °C/W to 23.8 and 6.2

 

 

 

 

°C/W respectively

 

 

 

 

Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and

 

 

 

 

4.0 °C/W respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

 

 

 

 

Updated Ordering Information Table

*C

418125

See ECN

NXR

Converted from Preliminary to Final.

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 18.

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 ∝A and 30 ∝A

 

 

 

 

to –30 ∝A and 5 ∝A.

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 ∝A and 5 ∝A

 

 

 

 

to –5 ∝A and 30 ∝A.

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18.

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table.

 

 

 

 

Updated Ordering Information Table.

*D

475009

See ECN

VKN

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*E

793579

See ECN

VKN

Added Part numbers CY7C1386F and CY7C1387F

 

 

 

 

Added footnote# 3 regarding Chip Enable

 

 

 

 

Updated Ordering Information table

Document Number: 38-05545 Rev. *E

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Contents 250 MHz 200 MHz 167 MHz Unit FeaturesSelection Guide Cypress Semiconductor CorporationLogic Block Diagram CY7C1386D/CY7C1386F 3 512K x Logic Block Diagram CY7C1387D/CY7C1387F 3 1M xPin Configurations Pin Tqfp Pinout 3 Chip Enables CY7C1386D 512K XCY7C1387D 1M x Pin Configurations Ball BGA Pinout 1 Chip Enable Pin Configurations Ball Fbga Pinout 3 Chip Enable Name Description Power supply inputs to the core of the devicePin Definitions Byte write select inputs, active LOW. Qualified withFunctional Overview Interleaved Burst Address Table Mode = Floating or VDD Linear Burst Address Table Mode = GNDZZ Mode Electrical Characteristics Operation Add. Used Truth Table for Read/Write 6 Function CY7C1386D/CY7C1386FFunction CY7C1387D/CY7C1387F TAP Controller State Diagram TAP Controller Block DiagramBypass Register TAP Instruction SetTAP AC Switching Characteristics TAP Timing3V TAP AC Output Load Equivalent 3V TAP AC Test Conditions5V TAP AC Test Conditions GND VIN VddqIdentification Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBall BGA Boundary Scan Order 14 Bit # Ball IDInternal M10 A10 B10M11 G10 F10 InternalOperating Range Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance Thermal ResistanceAC Test Loads and Waveforms Switching Characteristics Over the Operating Range 20 Description 250 200 167 Unit Parameter MinSwitching Waveforms Read Cycle TimingWrite Cycle Timing 26 AdscRead/Write Cycle Timing 26, 28 ZZ Mode Timing 30 Ordering Information CY7C1386D, CY7C1386F CY7C1387D, CY7C1387F Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Ball Fbga 13 x 15 x 1.4 mm Issue Date Orig. Description of Change Document HistoryDocument Number
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