Cypress CY7C1347G Ordering Information continued, Speed, Ordering Code, Package Type, Diagram

Page 17
Ordering Information (continued)

CY7C1347G

Table 7.

Ordering Information (continued)

 

 

Speed

Ordering Code

Package

Package Type

Operating

(MHz)

Diagram

Range

 

 

250

CY7C1347G-250AXC

51-85050

100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free

Commercial

 

 

 

 

 

 

CY7C1347G-250BGC

51-85115

119-Ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1347G-250BGXC

 

119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C1347G-250BZC

51-85180

165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1347G-250BZXC

 

165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C1347G-250AXI

51-85050

100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free

Industrial

 

 

 

 

 

 

CY7C1347G-250BGI

51-85115

119-Ball Ball Grid Array (14 x 22 x 2.4 mm)

 

 

 

 

 

 

 

CY7C1347G-250BGXI

 

119-Ball Ball Grid Array (14 x 22 x 2.4 mm) Pb-Free

 

 

 

 

 

 

 

CY7C1347G-250BZI

51-85180

165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm)

 

 

 

 

 

 

 

CY7C1347G-250BZXI

 

165-Ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free

 

 

 

 

 

 

Document #: 38-05516 Rev. *F

Page 17 of 22

[+] Feedback

Image 17
Contents CY7C1347G FeaturesSelection Guide Functional Description1ADDRESS Block DiagramREGISTER ADSCCY7C1347G PinoutsCY7C1347G Table 1. Pin Definitions CY7C1347GName DescriptionSingle Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Maximum Ratings Electrical CharacteristicsOperating Range VDDQCapacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continued19. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedPage 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document History PageDocument Number SubmissionPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products