Cypress CY7C1347G Document History Page, Document Number, Submission, Orig. of, Date, Change

Page 21

Document History Page

CY7C1347G

Document History Page

Document Title: CY7C1347G 4-Mbit (128K x 36) Pipelined Sync SRAM

Document Number: 38-05516

	REV.	ECN	Submission	Orig. of	Description of Change
	REV.	ECN	Date	Change	Description of Change
			Date	Change

	**	224364	See ECN	RKF	New data sheet

	*A	276690	See ECN	VBL	Changed TQFP package in Ordering Information section to lead-free TQFP
					Added comment of BG and BZ lead-free package availability
	*B	333625	See ECN	SYT	Removed 225 MHz and 100 MHz speed grades
					Modified Address Expansion balls in the pinouts for 100 TQFP Package as per
					JEDEC standards and updated the Pin Definitions accordingly
					Modified VOL, VOH test conditions
					Replaced TBDs for ΘJA and ΘJC to their respective values on the Thermal Resis-
					tance table
					Changed the package name for 100 TQFP from A100RA to A101
					Removed comment on the availability of BG lead-free package
					Updated the Ordering Information by shading and unshading MPNs as per
					availability
	*C	419256	See ECN	RXU	Converted from Preliminary to Final.
					Changed address of Cypress Semiconductor Corporation on Page #1 from “3901
					North First Street” to “198 Champion Court”
					Swapped typo CE2 and CE3 in the Truth Table column heading on Page #6
					Modified test condition from VIH < VDD to VIH < VDD.
					Modified test condition from VDDQ < VDD to VDDQ < VDD
					Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the
					Electrical Characteristics Table.
					Replaced Package Name column with Package Diagram in the Ordering Infor-
					mation table.
					Replaced Package Diagram of 51-85050 from A to B
					Replaced Package Diagram of 51-85180 from ** to *A
					Updated the Ordering Information.
	*D	480124	See ECN	VKN	Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND.
					Updated the Ordering Information table.
	*E	1078184	See ECN	VKN	Corrected write timing diagram on page 12

	*F	2633279	01/15/2009	NXR/AESA	Updated Ordering Information and data sheet template.

Document #: 38-05516 Rev. *F

Page 21 of 22

[+] Feedback

Image 21

Contents CY7C1347G FeaturesSelection Guide Functional Description1ADDRESS Block DiagramREGISTER ADSCCY7C1347G PinoutsCY7C1347G Table 1. Pin Definitions CY7C1347GName DescriptionSingle Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Maximum Ratings Electrical CharacteristicsOperating Range VDDQCapacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continuedFigure 7. Read/Write Cycle Timing16, 18 Page 14 of19. GW is HIGH ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedPACKAGE WEIGHT 0.475g Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mmPage 20 of Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document History PageDocument Number SubmissionPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products