Cypress CY7C1347G Document History Page, Document Number, Submission, Orig. of, Date, Change

Contents CY7C1347G FeaturesSelection Guide Functional Description1ADDRESS Block DiagramREGISTER ADSCCY7C1347G PinoutsCY7C1347G Table 1. Pin Definitions CY7C1347GName DescriptionSingle Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Maximum Ratings Electrical CharacteristicsOperating Range VDDQCapacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continuedFigure 7. Read/Write Cycle Timing16, 18 Page 14 of19. GW is HIGH ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedPACKAGE WEIGHT 0.475g Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mmPage 20 of Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document History PageDocument Number SubmissionPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products