Cypress CY7C1347G manual Switching Waveforms continued, Read/Write Cycle Timing16, 18, Page 14 of

Page 14

CY7C1347G

Switching Waveforms (continued)

A3	A4
tWES	tWEH

tDS tDH

tOELZ

D(A3)

Q(A4)

Q(A4+1)

Q(A4+2)

Q(A4+3)

D(A5) D(A6)

Back-to-Back READs

Single WRITE

BURST READ

Back-to-Back

WRITEs

DON’T CARE

UNDEFINED

Notes

18.The data bus (Q) remains in High-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.

19.GW is HIGH.

Document #: 38-05516 Rev. *F

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Contents Selection Guide FeaturesCY7C1347G Functional Description1REGISTER Block DiagramADDRESS ADSCPinouts CY7C1347GCY7C1347G Name CY7C1347GTable 1. Pin Definitions DescriptionSingle Write Accesses Initiated by ADSC Single Read AccessesSingle Write Accesses Initiated by ADSP Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Operating Range Electrical CharacteristicsMaximum Ratings VDDQThermal Resistance Electrical Characteristics continuedCapacitance AC Test Loads and WaveformsSwitching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16Switching Waveforms continued Figure 6. Write Cycle Timing1619. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZOrdering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmPackage Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mmPage 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Document Number Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM SubmissionWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products