Cypress CY7C1347G manual Block Diagram, + Feedback, Address, Register, Adsc, Dq D ,Dqp D

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Block Diagram

CY7C1347G

Block Diagram

A0, A1, A

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REGISTER

 

2

A[1:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

MODE

 

 

 

 

 

 

 

 

 

ADV

 

 

 

Q1

 

 

 

 

 

CLK

 

 

BURST

 

 

 

 

 

 

 

COUNTER

 

 

 

 

 

 

 

CLR

AND

Q0

 

 

 

 

 

ADSC

 

 

LOGIC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ADSP

 

 

 

 

 

 

 

 

 

 

DQD ,DQP D

 

 

DQD ,DQPD

 

 

 

 

 

BW D

BYTE

 

 

BYTE

 

 

 

 

 

 

WRITE REGISTER

 

 

WRITE DRIVER

 

 

 

 

 

 

DQC ,DQP C

 

 

DQC ,DQP C

 

 

 

 

 

BW C

BYTE

 

 

BYTE

 

 

 

OUTPUT

 

 

WRITE REGISTER

 

 

WRITE DRIVER

MEMORY

SENSE

OUTPUT

DQs

 

 

 

BUFFERS

 

 

 

 

 

ARRAY

REGISTERS

 

 

 

 

DQB ,DQP B

AMPS

E

DQP A

 

DQB ,DQP B

 

 

 

 

 

 

 

 

 

 

DQP B

BW B

BYTE

 

 

BYTE

 

 

 

 

 

 

 

 

 

 

DQP C

 

 

WRITE DRIVER

 

 

 

 

 

WRITE REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQP D

 

 

 

 

 

 

 

 

 

 

DQA ,DQP A

 

 

DQA ,DQP A

 

 

 

 

 

 

 

 

BYTE

 

 

 

 

 

BW A

BYTE

 

 

 

 

 

 

 

 

 

WRITE DRIVER

 

 

 

 

 

BWE

WRITE REGISTER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GW

 

 

 

 

 

 

 

 

INPUT

ENABLE

PIPELINED

 

 

 

 

 

REGISTERS

CE1

REGISTER

 

 

 

 

 

 

ENABLE

 

 

 

 

 

 

CE2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE3

 

 

 

 

 

 

 

 

 

OE

 

 

 

 

 

 

 

 

 

ZZ

SLEEP

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-05516 Rev. *F

Page 2 of 22

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Contents Selection Guide FeaturesCY7C1347G Functional Description1REGISTER Block DiagramADDRESS ADSCPinouts CY7C1347GCY7C1347G Name CY7C1347GTable 1. Pin Definitions DescriptionSingle Write Accesses Initiated by ADSC Single Read AccessesSingle Write Accesses Initiated by ADSP Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Operating Range Electrical CharacteristicsMaximum Ratings VDDQThermal Resistance Electrical Characteristics continuedCapacitance AC Test Loads and WaveformsSwitching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16Switching Waveforms continued Figure 6. Write Cycle Timing1619. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZOrdering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmPackage Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mmPage 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Document Number Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM SubmissionWorldwide Sales and Design Support Sales, Solutions, and Legal InformationPSoC Solutions Products