Cypress CY7C1347G manual Pin Definitions, Name, Description, + Feedback

CY7C1347G

Table 1. Pin Definitions

Name

IO

Description

A0,A1,A

Input-

Address Inputs Used

to Select One of the 128K Address Locations. Sampled at the rising edge

Synchronous

of the CLK if ADSP or

ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds

the 2-bit counter.

A,

B,

Input-

Byte Write Select Inputs, Active LOW. Qualified with

to conduct byte writes to the SRAM.

BW

BW

BWE

BWC,BWD

Synchronous

Sampled on the rising edge of CLK.

Input-

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global

GW

Synchronous

write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and

BWE)

.

Input-

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be

BWE

Synchronous

asserted LOW to conduct a byte write.

CLK

Input-Clock

Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

1

Input-

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2

CE

Synchronous

and

CE

3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when

a new external address is loaded.

CE2

Input-

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

1

CE

Synchronous

and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.

3

Input-

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with

1

CE

CE

Synchronous

and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.

Input-

Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW,

OE

Asynchronous

the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data

pins.

OE

is masked during the first clock of a read cycle when emerging from a deselected state.

Input-

Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically

ADV

Synchronous

increments the address in a burst cycle.

Input-

Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,

ADSP

Synchronous

addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the

burst counter. When

ADSP

and ADSC are both asserted, only ADSP is recognized. ASDP is ignored

when CE1 is deasserted HIGH.

Input-

Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,

ADSC

Synchronous

addresses presented

to the

device are captured in the address registers. A[1:0] are also loaded into the

burst counter. When

ADSP

and ADSC are both asserted, only ADSP is recognized.

ZZ

Input-

ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with

Asynchronous

data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an

internal pull down.

DQA, DQB

IO-

Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the

DQC, DQD

Synchronous

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

DQPA, DQPB,

addresses presented during the previous clock rise of the read cycle. The direction of the pins is

DQPC, DQPD

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs

are placed in a tri-state condition.

VDD

Power Supply

Power Supply Inputs to the Core of the Device

VSS

Ground

Ground for the Core of the Device

VDDQ

IO Power Supply

Power Supply for the IO circuitry

VSSQ

IO Ground

Ground for the IO circuitry

MODE

Input-

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left

Static

floating selects interleaved burst sequence. This is a strap pin and must remain static during device

operation. Mode pin has an internal pull up.

NC, NC/9M,

–

No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,

NC/18M,

NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the

NC/36M,

die.

NC/72M,

NC/144M,

NC/288M,

NC/576M,

NC/1G

Document #: 38-05516 Rev. *F

Page 5 of 22

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