Cypress CY7C1347G manual Switching Waveforms, Read Cycle Timing16, + Feedback

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Switching Waveforms

CY7C1347G

Switching Waveforms

Figure 5. Read Cycle Timing[16]

tCYC

CLK

tCH

tADS tADH

ADSP

ADSC

tAS tAH

tCL

tADS tADH

ADDRESS

GW, BWE,

BW [A:D]

CE

A1

tCES tCEH

A2

A3

tWES tWEH

Burst continued with

new base address

 

 

Deselect

 

cycle

tADVS tADVH

ADV

OE

tOEHZ

 

 

tCLZ

Data Out (Q)

High-Z

Q(A1)

 

 

tCO

 

 

Single READ

Figure 5. Read Cycle Timing[16]ADV suspends burst.

tOEV

tCO

 

 

 

 

 

tOELZ

tDOH

 

 

 

 

tCHZ

 

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A2 + 3)

Q(A2)

Q(A2 + 1)

 

 

 

 

 

Burst wraps around

 

 

 

BURST READ

 

to its

initial state

 

 

 

 

 

 

 

DON’T CARE

UNDEFINED

 

 

 

Note

16. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.

Document #: 38-05516 Rev. *F

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Contents Features CY7C1347GSelection Guide Functional Description1Block Diagram ADDRESSREGISTER ADSCPinouts CY7C1347GCY7C1347G CY7C1347G Table 1. Pin DefinitionsName DescriptionSingle Read Accesses Single Write Accesses Initiated by ADSPSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Electrical Characteristics Maximum RatingsOperating Range VDDQElectrical Characteristics continued CapacitanceThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16Switching Waveforms continued Figure 6. Write Cycle Timing16Figure 7. Read/Write Cycle Timing16, 18 Page 14 of19. GW is HIGH 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZOrdering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmPackage Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mmPACKAGE WEIGHT 0.475g Figure 11. 165-Ball FBGA 13 x 15 x 1.4 mmPage 20 of Document History Page Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAMDocument Number SubmissionSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products