Cypress CY7C1347G manual Switching Waveforms continued, Write Cycle Timing16, + Feedback

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Switching Waveforms (continued)

CY7C1347G

Switching Waveforms (continued)

Figure 6. Write Cycle Timing[16, 17]

CLK

ADSP

ADSC

ADDRESS

BWE, BW[A :B]

GW

CE

ADV

OE

Data In (D)

 

t CYC

 

 

 

 

 

 

 

 

 

 

 

tCH

tCL

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

ADSC extends burst

 

 

 

 

 

 

 

 

 

tADS

tADH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

tAH

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

 

A2

 

 

 

 

A3

 

 

 

 

Byte

write signals

are

 

 

 

 

 

 

 

 

 

ignored for first cycle when

 

 

 

 

 

tWES

tWEH

 

 

ADSP initiates burst

 

 

 

 

 

 

 

 

 

 

 

tWES tWEH

 

 

 

 

 

 

 

tCES

tCEH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tADVS

tADVH

 

 

 

 

 

 

 

ADV suspends burst

 

 

 

 

 

 

 

tDS

tDH

 

 

 

 

 

 

 

 

High-Z

t

D(A1)

D(A2)

D(A2 + 1)

D(A2 + 1)

D(A2 + 2)

D(A2 + 3)

D(A3)

D(A3 + 1)

D(A3 + 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

OEHZ

 

 

 

 

 

 

 

 

 

 

 

Data Out (Q)

BURST READ

Single WRITE

BURST WRITE

Extended BURST WRITE

DON’T CARE

UNDEFINED

Note

17. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWx LOW.

Document #: 38-05516 Rev. *F

Page 13 of 22

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Contents CY7C1347G FeaturesSelection Guide Functional Description1ADDRESS Block DiagramREGISTER ADSCCY7C1347G PinoutsCY7C1347G Table 1. Pin Definitions CY7C1347GName DescriptionSingle Write Accesses Initiated by ADSP Single Read AccessesSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Maximum Ratings Electrical CharacteristicsOperating Range VDDQCapacitance Electrical Characteristics continuedThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continuedPage 14 of Figure 7. Read/Write Cycle Timing16, 1819. GW is HIGH ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm PACKAGE WEIGHT 0.475gPage 20 of Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document History PageDocument Number SubmissionPSoC Solutions Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products