Cypress CY7C1347G manual 2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW

Contents Functional Description1 FeaturesCY7C1347G Selection GuideADSC Block DiagramADDRESS REGISTERCY7C1347G PinoutsCY7C1347G Description CY7C1347GTable 1. Pin Definitions NameFunctional Overview Single Read AccessesSingle Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 VDDQ Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Electrical Characteristics continuedCapacitance Thermal ResistanceSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continuedPage 14 of Figure 7. Read/Write Cycle Timing16, 1819. GW is HIGH ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm PACKAGE WEIGHT 0.475gPage 20 of Submission Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document NumberProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support