Cypress CY7C1347G manual Truth , 3, 4, 5

Page 8
Table 5. Truth Table [2, 3, 4, 5, 6]

CY7C1347G

Table 5. Truth Table [2, 3, 4, 5, 6]

(continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Add.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Next Cycle

CE1

CE2

 

CE3

ZZ

 

ADSP

ADSC

ADV

 

 

WRITE

 

OE

 

CLK

DQ

Used

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

X

X

 

X

L

 

H

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Continue Burst

Next

 

H

X

 

X

L

 

X

 

H

 

L

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

L

 

L-H

Q

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

H

 

H

 

L-H

Tri-State

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

X

X

 

X

L

 

H

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Cycle, Suspend Burst

Current

 

H

X

 

X

L

 

X

 

H

 

H

 

 

L

 

X

 

L-H

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table

6. Partial Truth Table for Read/Write[2, 7]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function

 

GW

 

 

BWE

 

 

BW

D

 

BW

C

 

BW

B

 

BW

A

Read

 

 

H

 

H

 

 

X

 

X

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read

 

 

H

 

L

 

 

H

 

H

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte A – DQA

 

H

 

L

 

 

H

 

H

 

H

 

L

Write Byte B – DQB

 

H

 

L

 

 

H

 

H

 

L

 

H

Write Bytes B, A

 

H

 

L

 

 

H

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte C– DQC

 

H

 

L

 

 

H

 

L

 

H

 

H

Write Bytes C, A

 

H

 

L

 

 

H

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes C, B

 

H

 

L

 

 

H

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes C, B, A

 

H

 

L

 

 

H

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte D– DQD

 

H

 

L

 

 

L

 

H

 

H

 

H

Write Bytes D, A

 

H

 

L

 

 

L

 

H

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, B

 

H

 

L

 

 

L

 

H

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, B, A

 

H

 

L

 

 

L

 

H

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, C

 

H

 

L

 

 

L

 

L

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, C, A

 

H

 

L

 

 

L

 

L

 

H

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, C, B

 

H

 

L

 

 

L

 

L

 

L

 

H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write All Bytes

 

H

 

L

 

 

L

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write All Bytes

 

L

 

X

 

 

X

 

X

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

7. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is based on which byte write is active.

Document #: 38-05516 Rev. *F

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Contents Features CY7C1347GSelection Guide Functional Description1Block Diagram ADDRESSREGISTER ADSCPinouts CY7C1347GCY7C1347G CY7C1347G Table 1. Pin DefinitionsName DescriptionSingle Read Accesses Single Write Accesses Initiated by ADSPSingle Write Accesses Initiated by ADSC Functional Overview2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 Electrical Characteristics Maximum RatingsOperating Range VDDQElectrical Characteristics continued CapacitanceThermal Resistance AC Test Loads and WaveformsSwitching Characteristics Switching Waveforms Figure 5. Read Cycle Timing16Switching Waveforms continued Figure 6. Write Cycle Timing1619. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of 21. DQs are in high-Z when exiting ZZ sleep mode ALL INPUTS except ZZOrdering Information Ordering Information continued Package Diagrams Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mmPackage Diagrams continued Figure 10. 119-Ball BGA 14 x 22 x 2.4 mmPage 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Document History Page Document Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAMDocument Number SubmissionSales, Solutions, and Legal Information PSoC SolutionsWorldwide Sales and Design Support Products