Cypress CY7C1347G manual Switching Characteristics

Page 11
Switching Characteristics

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1347G

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics

 

 

 

 

 

 

 

 

 

 

 

Over the Operating Range[14, 15]

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

Description

–250

–200

–166

–133

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tPOWER

 

V (Typical) to the first Access[10]

1

 

1

 

1

 

1

 

ms

 

 

 

 

DD

 

 

 

 

 

 

 

 

 

 

 

Clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC

 

Clock Cycle Time

4.0

 

5.0

 

6.0

 

7.5

 

ns

 

 

tCH

 

Clock HIGH

1.7

 

2.0

 

2.5

 

3.0

 

ns

 

 

tCL

 

Clock LOW

1.7

 

2.0

 

2.5

 

3.0

 

ns

 

 

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

 

Data Output Valid After CLK Rise

 

2.6

 

2.8

 

3.5

 

4.0

ns

 

 

tDOH

 

Data Output Hold After CLK Rise

1.0

 

1.0

 

1.5

 

1.5

 

ns

 

 

tCLZ

 

Clock to Low-Z[11, 12, 13]

0

 

0

 

0

 

0

 

ns

 

 

tCHZ

 

Clock to High-Z[11, 12, 13]

 

2.6

 

2.8

 

3.5

 

4.0

ns

 

 

tOEV

 

 

 

LOW to Output Valid

 

2.6

 

2.8

 

3.5

 

4.5

ns

 

OE

 

tOELZ

 

 

 

LOW to Output Low-Z[11, 12, 13]

0

 

0

 

0

 

0

 

ns

 

OE

 

tOEHZ

 

 

 

HIGH to Output High-Z[11, 12, 13]

 

2.6

 

2.8

 

3.5

 

4.0

ns

 

OE

 

Setup Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAS

 

Address Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

 

tADS

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

ADSC,

ADSP

 

tADVS

 

 

 

 

 

Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

ADV

 

tWES

 

 

 

 

 

 

 

 

 

 

 

 

 

Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

GW,

BWE,

BW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

tDS

 

Data Input Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

 

tCES

 

Chip Enable Setup Before CLK Rise

1.2

 

1.2

 

1.5

 

1.5

 

ns

 

 

Hold Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAH

 

Address Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

 

tADH

 

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

ADSP,

ADSC

 

tADVH

 

 

 

 

Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

ADV

 

tWEH

 

 

 

 

 

 

 

 

 

 

 

 

 

Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

GW,

BWE,

BW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X

 

 

 

 

 

 

 

 

 

 

 

tDH

 

Data Input Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

 

tCEH

 

Chip Enable Hold After CLK Rise

0.3

 

0.5

 

0.5

 

0.5

 

ns

 

 

Notes

10.This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated.

11.tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads and Waveforms on page 10. Transition is measured ±200 mV from steady-state voltage.

12.At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions.

13.This parameter is sampled and not 100% tested.

14.Timing references level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V on all data sheets.

15.Test conditions shown in (a) of AC Test Loads and Waveforms on page 10 unless otherwise noted.

Document #: 38-05516 Rev. *F

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Contents Functional Description1 FeaturesCY7C1347G Selection GuideADSC Block DiagramADDRESS REGISTERCY7C1347G PinoutsCY7C1347G Description CY7C1347GTable 1. Pin Definitions NameFunctional Overview Single Read AccessesSingle Write Accesses Initiated by ADSP Single Write Accesses Initiated by ADSC2. X = “Do Not Care.” H = Logic HIGH, L = Logic LOW Table 5. Truth Table 2, 3, 4, 5 VDDQ Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Loads and Waveforms Electrical Characteristics continuedCapacitance Thermal ResistanceSwitching Characteristics Figure 5. Read Cycle Timing16 Switching WaveformsFigure 6. Write Cycle Timing16 Switching Waveforms continued19. GW is HIGH Figure 7. Read/Write Cycle Timing16, 18Page 14 of ALL INPUTS except ZZ 21. DQs are in high-Z when exiting ZZ sleep modeOrdering Information Ordering Information continued Figure 9. 100-Pin Thin Plastic Quad Flatpack 14 x 20 x 1.4 mm Package DiagramsFigure 10. 119-Ball BGA 14 x 22 x 2.4 mm Package Diagrams continuedPage 20 of PACKAGE WEIGHT 0.475gFigure 11. 165-Ball FBGA 13 x 15 x 1.4 mm Submission Document History PageDocument Title CY7C1347G 4-Mbit 128K x 36 Pipelined Sync SRAM Document NumberProducts Sales, Solutions, and Legal InformationPSoC Solutions Worldwide Sales and Design Support