Cypress CY14B108N, CY14B108L Truth Table For Sram Operations, Inputs/Outputs Mode Power, High Z

Page 16

 

 

 

 

 

 

 

 

 

 

PRELIMINARY

CY14B108L, CY14B108N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Truth Table For SRAM Operations

 

 

 

 

 

 

 

should remain HIGH for SRAM Operations.

 

 

 

 

 

HSB

 

 

 

 

 

For x8 Configuration

 

 

 

 

 

 

 

 

 

CE

 

 

WE

 

 

OE

 

Inputs/Outputs[2]

Mode

 

Power

 

 

 

H

 

 

X

 

X

High Z

Deselect/Power down

 

Standby

 

 

 

 

L

 

 

H

 

L

Data Out (DQ0–DQ7);

Read

 

Active

 

 

 

 

L

 

 

H

 

H

High Z

Output Disabled

 

Active

 

 

 

 

L

 

 

L

 

X

Data in (DQ0–DQ7);

Write

 

Active

 

 

For x16 Configuration

 

CE

 

 

WE

 

 

OE

 

 

BHE

[3]

 

BLE

[3]

Inputs/Outputs[2]

Mode

Power

 

H

 

 

X

 

 

X

 

 

X

 

X

High-Z

Deselect/Power down

Standby

 

L

 

 

X

 

 

X

 

 

H

 

H

High-Z

Output Disabled

Active

 

L

 

 

H

 

 

L

 

 

L

 

L

Data Out (DQ0–DQ15)

Read

Active

 

L

 

 

H

 

 

L

 

 

H

 

L

Data Out (DQ0–DQ7);

Read

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ8–DQ15in High-Z

 

 

 

L

 

 

H

 

 

L

 

 

L

 

H

Data Out (DQ8–DQ15);

Read

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ0–DQ7in High-Z

 

 

 

L

 

 

H

 

 

H

 

 

L

 

L

High-Z

Output Disabled

Active

 

L

 

 

H

 

 

H

 

 

H

 

L

High-Z

Output Disabled

Active

 

L

 

 

H

 

 

H

 

 

L

 

H

High-Z

Output Disabled

Active

 

L

 

 

L

 

 

X

 

 

L

 

L

Data In (DQ0–DQ15)

Write

Active

 

L

 

 

L

 

 

X

 

 

H

 

L

Data In (DQ0–DQ7);

Write

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ8–DQ15in High-Z

 

 

 

L

 

 

L

 

 

X

 

 

L

 

H

Data In (DQ8–DQ15);

Write

Active

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ0–DQ7in High-Z

 

 

Document #: 001-45523 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale Output Enable, Active LOW . The active LO W Byte High Enable, Active LOW . Controls DQ 15 DQByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the DeviceDevice Operation Sram ReadSram Write AutoStore OperationSoftware Store Hardware Recall Power UpSoftware Recall Store Mode SelectionRecall Preventing AutoStore Data ProtectionNoise Considerations Best PracticesDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthTruth Table For Sram Operations Inputs/Outputs Mode PowerHigh Z Ordering Information CY14B108N-ZSP20XCTCY14B108N-ZSP20XIT CY14B108N-ZSP25XCTCY14B108N-ZSP45XCT CY14B108N-ZSP45XITPart Numbering Nomenclature CY 14 B 108L-ZS P 20 X C TZS Tsop NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Gvch Document HistoryGVCH/PYRS Sales, Solutions, and Legal Information USB