Cypress CY14B108L, CY14B108N manual Ball Fbga 6 mm x 10 mm x 1.2 mm

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PRELIMINARY	CY14B108L, CY14B108N

Figure 16. 48-Ball FBGA - 6 mm x 10 mm x 1.2 mm (51-85128)

TOP VIEW

A1 CORNER

1 2 3 4 5 6

BOTTOM VIEW

A1 CORNER

0.36

6.00±0.10

SEATING PLANE

1.20 MAX

10.00±0.10

Document #: 001-45523 Rev. *B

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationPinouts Top ViewNot to scale Byte High Enable, Active LOW . Controls DQ 15 DQ Output Enable, Active LOW . The active LO WByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the DeviceSram Read Device OperationSram Write AutoStore OperationHardware Recall Power Up Software StoreSoftware Recall Mode Selection StoreRecall Data Protection Preventing AutoStoreNoise Considerations Best PracticesMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled STORE/RECALL Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthInputs/Outputs Mode Power Truth Table For Sram OperationsHigh Z CY14B108N-ZSP20XCT Ordering InformationCY14B108N-ZSP20XIT CY14B108N-ZSP25XCTCY14B108N-ZSP45XIT CY14B108N-ZSP45XCTCY 14 B 108L-ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Document History GvchGVCH/PYRS USB Sales, Solutions, and Legal Information