Cypress CY14B108L, CY14B108N manual AutoStore/Power Up Recall

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PRELIMINARY

 

 

CY14B108L, CY14B108N

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AutoStore/Power Up RECALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameters

 

 

Description

 

20 ns

 

25 ns

 

45 ns

Unit

 

 

Min

 

Max

Min

 

Max

Min

 

Max

 

 

 

 

 

 

 

 

 

 

 

t

[17]

 

Power Up RECALL Duration

 

 

20

 

 

20

 

 

20

ms

HRECALL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSTORE [18]

 

STORE Cycle Duration

 

 

8

 

 

8

 

 

8

ms

tDELAY [19]

 

Time Allowed to Complete SRAM Cycle

 

 

20

 

 

25

 

 

25

ns

VSWITCH

 

 

Low Voltage Trigger Level

 

 

2.65

 

 

2.65

 

 

2.65

V

tVCCRISE

 

 

VCC Rise Time

150

 

 

150

 

 

150

 

 

μs

VHDIS[10]

 

 

 

Output Driver Disable Voltage

 

 

1.9

 

 

1.9

 

 

1.9

V

 

 

HSB

 

 

 

tLZHSB

 

 

 

To Output Active Time

 

 

5

 

 

5

 

 

5

μs

 

 

HSB

 

 

 

tHHHD

 

 

 

High Active Time

 

 

500

 

 

500

 

 

500

ns

 

 

HSB

 

 

 

Switching Waveforms

Figure 10. AutoStore or Power Up RECALL[20]

VSWITCH

 

 

 

 

VHDIS

 

 

 

 

VVCCRISE

Note18

t

Note18

t

 

 

STORE

 

STORE

 

tHHHD

 

tHHHD

Note21

 

 

 

HSB OUT

 

 

tDELAY

 

 

 

 

 

 

tLZHSB

 

t

 

Autostore

 

 

LZHSB

 

 

 

 

 

 

tDELAY

 

 

 

POWER-

 

 

 

 

UP

 

 

 

 

RECALL

tHRECALL

 

tHRECALL

 

 

 

 

 

Read & Write

Inhibited

(RWI)

POWER-UP Read & Write

BROWN

POWER-UP

Read & Write

POWER

RECALL

OUT

RECALL

 

DOWN

 

Autostore

 

 

Autostore

Notes

17.tHRECALL starts from the time VCC rises above VSWITCH.

18.If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.

19.On a Hardware STORE, Software STORE / RECALL, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time tDELAY.

20.Read and Write cycles are ignored during STORE, RECALL, and while VCC is below VSWITCH.

21.HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.

Document #: 001-45523 Rev. *B

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Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationTop View PinoutsNot to scale Byte High Enable, Active LOW . Controls DQ 15 DQ Output Enable, Active LOW . The active LO WByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the DeviceSram Read Device OperationSram Write AutoStore OperationSoftware Store Hardware Recall Power UpSoftware Recall Store Mode SelectionRecall Data Protection Preventing AutoStoreNoise Considerations Best PracticesMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled STORE/RECALL Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthTruth Table For Sram Operations Inputs/Outputs Mode PowerHigh Z CY14B108N-ZSP20XCT Ordering InformationCY14B108N-ZSP20XIT CY14B108N-ZSP25XCTCY14B108N-ZSP45XIT CY14B108N-ZSP45XCTCY 14 B 108L-ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Gvch Document HistoryGVCH/PYRS USB Sales, Solutions, and Legal Information
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