Cypress CY14B108L, CY14B108N manual Hardware Recall Power Up, Software Store, Software Recall

Page 5

PRELIMINARY

CY14B108L, CY14B108N

 

STORE operation is completed, the CY14B108L/CY14B108N remains disabled until the HSB pin returns HIGH. Leave the HSB unconnected if it is not used.

Hardware RECALL (Power Up)

During power up or after any low power condition (VCC< VSWITCH), an internal RECALL request is latched. When VCC again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. During this time, HSB is driven LOW by the HSB driver.

Software STORE

Transfer data from the SRAM to the nonvolatile memory with a software address sequence. The CY14B108L/CY14B108N Software STORE cycle is initiated by executing sequential CE controlled read cycles from six specific address locations in exact order. During the STORE cycle an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. After a STORE cycle is initiated, further input and output are disabled until the cycle is completed.

Because a sequence of READs from specific addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence, or the sequence is aborted and no STORE or RECALL takes place.

To initiate the Software STORE cycle, the following read sequence must be performed.

1.Read Address 0x4E38 Valid READ

2.Read Address 0xB1C7 Valid READ

3.Read Address 0x83E0 Valid READ

4.Read Address 0x7C1F Valid READ

5.Read Address 0x703F Valid READ

6.Read Address 0x8FC0 Initiate STORE Cycle

The software sequence may be clocked with CE controlled reads or OE controlled reads. After the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. HSB is driven LOW. It is important to use read cycles and not write cycles in the sequence, although it is not necessary that OE be LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is activated again for the read and write operation.

Software RECALL

Transfer the data from the nonvolatile memory to the SRAM with a software address sequence. A Software RECALL cycle is initiated with a sequence of read operations in a manner similar to the Software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled read operations must be performed.

1.Read Address 0x4E38 Valid READ

2.Read Address 0xB1C7 Valid READ

3.Read Address 0x83E0 Valid READ

4.Read Address 0x7C1F Valid READ

5.Read Address 0x703F Valid READ

6.Read Address 0x4C63 Initiate RECALL Cycle

Internally, RECALL is a two-step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for read and write operations. The RECALL operation does not alter the data in the nonvolatile elements.

Document #: 001-45523 Rev. *B

Page 5 of 24

[+] Feedback

Image 5
Contents Logic Block Diagram1, 2 FeaturesFunctional Description Cypress Semiconductor CorporationNot to scale PinoutsTop View Byte High Enable, Active LOW . Controls DQ 15 DQ Output Enable, Active LOW . The active LO WByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the DeviceSram Read Device OperationSram Write AutoStore OperationSoftware Recall Hardware Recall Power UpSoftware Store Recall Mode SelectionStore Data Protection Preventing AutoStoreNoise Considerations Best PracticesMaximum Ratings DC Electrical CharacteristicsOperating Range RangeCapacitance Data Retention and EnduranceThermal Resistance AC Test ConditionsSwitching Waveforms AC Switching CharacteristicsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled STORE/RECALL Cycle Hardware Store Cycle To Output Active Time when write latch not setDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthHigh Z Inputs/Outputs Mode PowerTruth Table For Sram Operations CY14B108N-ZSP20XCT Ordering InformationCY14B108N-ZSP20XIT CY14B108N-ZSP25XCTCY14B108N-ZSP45XIT CY14B108N-ZSP45XCTCY 14 B 108L-ZS P 20 X C T Part Numbering NomenclatureZS Tsop NvsramPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Document HistoryGvch USB Sales, Solutions, and Legal Information