Cypress CY14B108L, CY14B108N Hardware Store Cycle, Description 20 ns 25 ns 45 ns Unit Min Max

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PRELIMINARY

CY14B108L, CY14B108N

Hardware STORE Cycle

Parameters

Description

20 ns

25 ns

45 ns

Unit

Min

Max

Min

Max

Min

Max

tDHSB

To Output Active Time when write latch not set

20

25

25

ns

HSB

tPHSB

Hardware STORE Pulse Width

15

15

15

ns

tSS [24, 25]

Soft Sequence Processing Time

100

100

100

μs

Switching Waveforms

Figure 13. Hardware STORE Cycle[18]

Write latch set

HSB (IN)

HSB (OUT)

DQ (Data Out)

RWI

tPHSB

tDELAY

tSTORE

tHHHD

tLZHSB

Write latch not set

tPHSB

HSB (IN)

HSB (OUT)

tDELAY

tDHSB

HSB pin is driven high to VCC only by Internal 100kOhm resistor,

HSB driver is disabled

SRAM is disabled as long as HSB (IN) is driven low.

tDHSB

RWI

Figure 14. Soft Sequence Processing[24, 25]

	Soft Sequence		tSS	Soft Sequence		tSS
	Command			Command
Address	Address #1	Address #6		Address #1	Address #6
	tSA		tCW		tCW
CE
VCC

Notes

24.This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.

25.Commands such as STORE and RECALL lock out IO until operation is complete which further increases this time. See the specific command.

Document #: 001-45523 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionPinouts Top ViewNot to scale Power Supply Inputs to the Device Output Enable, Active LOW . The active LO WByte High Enable, Active LOW . Controls DQ 15 DQ Byte Low Enable, Active LOW . Controls DQ 7 DQAutoStore Operation Device OperationSram Read Sram WriteHardware Recall Power Up Software StoreSoftware Recall Mode Selection StoreRecall Best Practices Preventing AutoStoreData Protection Noise ConsiderationsRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled STORE/RECALL Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min MaxInputs/Outputs Mode Power Truth Table For Sram OperationsHigh Z CY14B108N-ZSP25XCT Ordering InformationCY14B108N-ZSP20XCT CY14B108N-ZSP20XITCY14B108N-ZSP45XIT CY14B108N-ZSP45XCTNvsram Part Numbering NomenclatureCY 14 B 108L-ZS P 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Document History GvchGVCH/PYRS USB Sales, Solutions, and Legal Information