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| PRELIMINARY | CY14B108L, CY14B108N | |||||||
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Table 2. Mode Selection |
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| [3] | A15 - A0[5] | Mode | IO | Power | |
| CE |
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| WE |
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| OE, | BHE, | BLE | ||||||||||
| H |
| X |
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| X | X | Not Selected | Output High Z | Standby | ||||||
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| L |
| H |
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| L | X | Read SRAM | Output Data | Active | ||||||
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| L |
| L |
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| X | X | Write SRAM | Input Data | Active | ||||||
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| L |
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| L | 0x4E38 | Read SRAM | Output Data | Active[6] | ||||||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x8B45 | AutoStore | Output Data |
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| Disable |
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| L |
| H |
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| L | 0x4E38 | Read SRAM | Output Data | Active[6] | ||||||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x4B46 | AutoStore Enable | Output Data |
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| L |
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| L | 0x4E38 | Read SRAM | Output Data | Active ICC2[6] | ||||||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x8FC0 | Nonvolatile | Output High Z |
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| STORE |
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| L | 0x4E38 | Read SRAM | Output Data | Active[6] | ||||||
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| 0xB1C7 | Read SRAM | Output Data |
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| 0x83E0 | Read SRAM | Output Data |
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| 0x7C1F | Read SRAM | Output Data |
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| 0x703F | Read SRAM | Output Data |
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| 0x4C63 | Nonvolatile | Output High Z |
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| RECALL |
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Notes
5.While there are 20 address lines on the CY14B108L (19 address lines on the CY14B108N), only the 13 address lines (A14 - A2) are used to control software modes. Rest of the address lines are don’t care.
6.The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document #: | Page 6 of 24 |
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