Cypress CY14B108N, CY14B108L manual Pinouts, Top View, Not to scale

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PRELIMINARY	CY14B108L, CY14B108N

Pinouts

		Figure 1. Pin Diagram - 48 FBGA
	48-FBGA	48-FBGA
	(x8)	(x16)
	Top View	(x16)
	Top View	Top View
	(not to scale)	(not to scale)

1	2		3	4	5	6
NC	OE		A0	A1	A2	NC	A
NC	NC		A3	A4	CE	NC	B
DQ0	NC		A5	A6	NC	DQ4	C
VSS	DQ		A	A7	DQ	VCC	D
	1		17		5
VCC	DQ	2	V	A16	DQ	VSS	E
		2	CAP		6
DQ3	NC		A14	A15	NC	DQ7	F
NC[4]	HSB		A12	A13	WE	NC	G
A18	A8		A9	A10	A11	A19	H

1	2	3	4	5	6
BLE	OE	A0	A1	A2	NC	A
DQ8	BHE	A	A	CE	DQ	B
		3	4		0
DQ9	DQ10	A5	A6	DQ1	DQ2	C
VSS	DQ	A	A7	DQ	VCC	D
	11	17		3
VCC	DQ	V	A16	DQ	VSS	E
	12	CAP		4
DQ14	DQ13	A14	A15	DQ5	DQ6	F
DQ15	HSB	A12	A13	WE	DQ7	G
A18	A8	A9	A10	A11	NC[4]	H

Figure 2. Pin Diagram - 44/54-Pin TSOP II

44-TSOP II

(x8)

54-TSOP II

(x16)

NC

NC[4]

A0

A1

A2

A3

A4

CE

DQ0

DQ1

VCC

VSS

DQ2

DQ3

WE A5 A6 A7 A8 A9

NC

NC

1

2

3

4

5

6

7

8

9

10

11

12Top View

13(not to scale)

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

HSB

NC

A19 A18

A17

A16

A15

OE

DQ7 DQ6

VSS VCC

DQ5 DQ4

VCAP

A14

A13

A12

A11

A10

NC NC

		NC							1		54					HSB
[4]											53					A18
NC									2

		A0							3		52					A17


		A1							4		51						A16


		A2							5		50						A15


		A3							6		49					OE

		A4							7		48					BHE

		CE							8		47						BLE


DQ0									9		46					DQ15


DQ1									10		45					DQ14

DQ2									11		44					DQ13

DQ3									12		43					DQ12

VCC									13	Top View	42						VSS

VSS									14	(not to scale) 41							VCC

DQ4									15		40						DQ11


DQ5									16		39						DQ10

DQ6									17		38						DQ9

											37
DQ7									18								DQ8

											36
	WE								19								VCAP

											35
		A5							20								A14

											34
		A6							21								A13
											33
		A7							22								A12
											32
		A8							23								A11

											31
		A9							24								A10
											30
	NC								25							NC
	NC								26		29					NC

	NC								27		28					NC

Notes

4. Address expansion for 16 Mbit. NC pin not connected to die.

Document #: 001-45523 Rev. *B

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Contents Functional Description FeaturesLogic Block Diagram1, 2 Cypress Semiconductor CorporationNot to scale PinoutsTop View Byte Low Enable, Active LOW . Controls DQ 7 DQ Output Enable, Active LOW . The active LO WByte High Enable, Active LOW . Controls DQ 15 DQ Power Supply Inputs to the DeviceSram Write Device OperationSram Read AutoStore OperationSoftware Recall Hardware Recall Power UpSoftware Store Recall Mode SelectionStore Noise Considerations Preventing AutoStoreData Protection Best PracticesOperating Range DC Electrical CharacteristicsMaximum Ratings RangeThermal Resistance Data Retention and EnduranceCapacitance AC Test ConditionsParameters Sram Read Cycle AC Switching CharacteristicsSwitching Waveforms Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle Description 20 ns 25 ns 45 ns Unit Min Max To Output Active Time when write latch not setHardware Store Cycle Hardware Store Pulse WidthHigh Z Inputs/Outputs Mode PowerTruth Table For Sram Operations CY14B108N-ZSP20XIT Ordering InformationCY14B108N-ZSP20XCT CY14B108N-ZSP25XCTCY14B108N-ZSP45XCT CY14B108N-ZSP45XITZS Tsop Part Numbering NomenclatureCY 14 B 108L-ZS P 20 X C T NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Document HistoryGvch Sales, Solutions, and Legal Information USB