Cypress CY14B108L, CY14B108N manual Sram Read Cycle #2 CE and OE Controlled3, 11

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PRELIMINARY	CY14B108L, CY14B108N

Figure 6. SRAM Read Cycle #2: CE and OE Controlled[3, 11, 15]

Address

Address Valid

Notes

16. CE or WE must be >VIH during address transitions.

Document #: 001-45523 Rev. *B

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Contents Cypress Semiconductor Corporation FeaturesLogic Block Diagram1, 2 Functional DescriptionNot to scale PinoutsTop View Power Supply Inputs to the Device Output Enable, Active LOW . The active LO WByte High Enable, Active LOW . Controls DQ 15 DQ Byte Low Enable, Active LOW . Controls DQ 7 DQAutoStore Operation Device OperationSram Read Sram WriteSoftware Recall Hardware Recall Power UpSoftware Store Recall Mode SelectionStore Best Practices Preventing AutoStoreData Protection Noise ConsiderationsRange DC Electrical CharacteristicsMaximum Ratings Operating RangeAC Test Conditions Data Retention and EnduranceCapacitance Thermal ResistanceSram Write Cycle AC Switching CharacteristicsSwitching Waveforms Parameters Sram Read CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 Parameters Description 20 ns 25 ns 45 ns Unit Min Max AutoStore/Power Up RecallSoftware Controlled STORE/RECALL Cycle Hardware Store Pulse Width To Output Active Time when write latch not setHardware Store Cycle Description 20 ns 25 ns 45 ns Unit Min MaxHigh Z Inputs/Outputs Mode PowerTruth Table For Sram Operations CY14B108N-ZSP25XCT Ordering InformationCY14B108N-ZSP20XCT CY14B108N-ZSP20XITCY14B108N-ZSP45XIT CY14B108N-ZSP45XCTNvsram Part Numbering NomenclatureCY 14 B 108L-ZS P 20 X C T ZS TsopPin Tsop II Package DiagramsBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 GVCH/PYRS Document HistoryGvch USB Sales, Solutions, and Legal Information