Cypress CY14B108N, CY14B108L manual Sram Write Cycle #2

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		PRELIMINARY		CY14B108L, CY14B108N
				CY14B108L, CY14B108N

		Figure 8. SRAM Write Cycle #2:
				Controlled[3, 14, 15, 16]
			CE	Controlled[3, 14, 15, 16]

Address

CE

BHE, BLE

WE

Data Input

Data Output

	tWC
	Address Valid
tSA	tSCE	tHA
	tBW
	tPWE
	tSD	tHD
	Input Data Valid
	High Impedance

Figure 9. SRAM Write Cycle #3: BHE and BLE Controlled[3, 14, 15, 16]
	tWC
Address	Address Valid
	tSCE
CE
tSA	tBW	tHA
BHE, BLE
	tAW
	tPWE
WE
	tSD	tHD
Data Input	Input Data Valid
	High Impedance
Data Output

Document #: 001-45523 Rev. *B

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Contents Features Logic Block Diagram1, 2Functional Description Cypress Semiconductor CorporationPinouts Top ViewNot to scale Output Enable, Active LOW . The active LO W Byte High Enable, Active LOW . Controls DQ 15 DQByte Low Enable, Active LOW . Controls DQ 7 DQ Power Supply Inputs to the DeviceDevice Operation Sram ReadSram Write AutoStore OperationHardware Recall Power Up Software StoreSoftware Recall Mode Selection StoreRecall Preventing AutoStore Data ProtectionNoise Considerations Best PracticesDC Electrical Characteristics Maximum RatingsOperating Range RangeData Retention and Endurance CapacitanceThermal Resistance AC Test ConditionsAC Switching Characteristics Switching WaveformsParameters Sram Read Cycle Sram Write CycleSram Read Cycle #2 CE and OE Controlled3, 11 Sram Write Cycle #2 AutoStore/Power Up Recall Parameters Description 20 ns 25 ns 45 ns Unit Min MaxSoftware Controlled STORE/RECALL Cycle To Output Active Time when write latch not set Hardware Store CycleDescription 20 ns 25 ns 45 ns Unit Min Max Hardware Store Pulse WidthInputs/Outputs Mode Power Truth Table For Sram OperationsHigh Z Ordering Information CY14B108N-ZSP20XCTCY14B108N-ZSP20XIT CY14B108N-ZSP25XCTCY14B108N-ZSP45XCT CY14B108N-ZSP45XITPart Numbering Nomenclature CY 14 B 108L-ZS P 20 X C TZS Tsop NvsramPackage Diagrams Pin Tsop IIBall Fbga 6 mm x 10 mm x 1.2 mm 51-85160 Document History GvchGVCH/PYRS Sales, Solutions, and Legal Information USB