Time Out Interrupts, Internal Registers

Chapter 4 – SocketModem Parallel Interface – A Programmer’s Description

Time Out Interrupts

The interrupts are enabled by IER bits 0-3. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the SocketModem will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing operations.

The LSR register provides the current singular highest priority interrupt only. A condition can exist where a higher priority interrupt may mask the lower priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority interrupt(s) be reflected in the status register. Servicing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly.

Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-3). The receiver issues an interrupt after the number of characters received have reached the programmed trigger level. In this case the MMM FIFO may hold more characters than the programmed trigger level. Following the removal of a data byte, the user should recheck LSR bit-0 for additional characters. A Receive Time Out will not occur if the receive FIFO is empty. The time out counter is reset at the center of each stop bit received or each time the receive holding register (RHR) is read.

Register Functional Descriptions

The following table delineates the assigned bit functions for the twelve internal registers. The assigned bit functions are more fully defined in the following paragraphs.

Internal Registers

A2 A1 A0			Register	BIT-7	BIT-6	BIT-5	BIT-4	BIT-3	BIT-2	BIT-1	BIT-0
			[Default]
			Note *3
General Register Set: Note 1*
0	0	0	RBR [XX]	Bit-7	Bit-6	Bit-5	Bit-4	Bit-3	Bit-2	Bit-1	Bit-0
0	0	0	THR [XX]	Bit-7	Bit-6	Bit-5	Bit-4	Bit-3	Bit-2	Bit-1	Bit-0
0	0	1	IER [00]	0	0	0	0	Modem	Receive	Transmit	Receive
								Status	Line	Holding	Holding
								Interrupt	Status	Register	Register
									interrupt	interrupt	interrupt
0	1	0	IIR [XX]	FIFO	FIFO	0	0	Interrupt	Interrupt	Interrupt	Interrupt
				enable	enable			ID	ID	ID	Pending
0	1	0	FCR [00]	RX	RX	Detect	TX	DMA	XMIT	RCVR	FIFO
				Trigger	trigger	change	FIFO	mode	FIFO	FIFO	enable
				(MSB)	(LSB)	in FCR	overrun	select	reset	reset
							bit
0	1	1	LCR [00]	Divisor	Set	Stick	Even	Parity	0	Word	Word
				latch	break	parity	parity	enable		length	length
				access						bit-1	bit-0
				(DLAB)
1	0	0	MCR [00]	0	0	0	Loop	INT	OUT 1	-RTS	-DTR
							back	enable

1 0 1

LSR [60] RX FIFO data error

TX empty

THR empty

THR	Break	Framing	Parity
Empty	interrupt	error	error

Overrun error

Receive data ready

1	1	0	MSR [X0]	CD	RI	DSR	CTS	Delta	Delta	Delta	Delta
								-CD	-RI	-DSR	-CTS
1	1	1	SCR [FF]	Bit-7	Bit-6	Bit-5	Bit-4	Bit-3	Bit-2	Bit-1	Bit-0
Special Register Set: Note *2
0	0	0	DLL [00]	Bit-7	Bit-6	Bit-5	Bit-4	Bit-3	Bit-2	Bit-1	Bit-0
0	0	1	DLM [00]	Bit-7	Bit-6	Bit-5	Bit-4	Bit-3	Bit-2	Bit-1	Bit-0

Note 1* The General Register set is accessible only when DS is a logic 0.

Note 2* The Baud Rate register set is accessible only when DS is a logic 0 and LCR bit-7 is a logic 1. Note 3* The value between the square brackets represents the register's initialized HEX value, X = N/A.

SocketModem Global MT5634SMI Developer’s Guide